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ics for communications enhanced serial communication controller with 8 channels escc8 sab 82538 saf 82538 version 2.2 users manual 03.95
edition 03.95 this edition was realized using the software system framemaker ? . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1995. all rights reserved. attention please! as far as patents or other rights of third par- ties are concerned, liability is only assumed for components, not for applications, pro- cesses and circuits implemented within com- ponents or assemblies. the information describes the type of compo- nent and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for in- formation on the types in question please contact your nearest siemens office, semi- conductor group. siemens ag is an approved cecc manufac- turer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us un- sorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the ex- press written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effec- tiveness of that device or system. 2 life support devices or systems are in- tended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is rea- sonable to assume that the health of the user may be endangered.
data classification maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 ?c and the given supply voltage. operating range in the operating range the functions given in the circuit description are fulfilled. for detailed technical information about "processing guidelines" and "quality assurance" for ics, see our "product overview" . sab 82538 saf 82538 revision history: current version: 03.95 previous version: users manual 01.94 page (in version 01.94) page (in new version subjects (changes since last revision) 11 11 v dd and v ss pin configuration 13 13 rd/ ds description 14 14 res pin number 19 19 dackx description 22 22 v dd and v ss numbers 54 54 transparent mode 1, address recognition 58 58 transmitter interrupts, figure 21 61 61 transmitter interrupts, figures 23/24 65 65 transmitter interrupts, figures 28/29 86 86 note in description of clock mode 5 86 86 cd-signal, figure 35 110 111 interrupt driven reception sequence, figure 47 113 114 ccr4 register addresses 126 127 rhcr register description 127 129 xbc register description 145 147/148 xmr interrupt description 157 159 rfrd command description 164 166 rbc register description 178 181 tcd interrupt description 190 194 rfrd command description 198 201 rbc register description 211 214 tcd interrupt description 228 231 timings t p (drt) , t su (ie) 236 239 timing t su (ie) 238 241 timing t p (pv-int) 241 244 number of timing t c (xc) C C minor misprints
semiconductor group 4 general information introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.1 pin definitions and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.4 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.4.1 general aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.4.2 environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.4.2.1 escc8 with sab 80188 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.4.2.2 escc8 with 80386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.4.2.3 escc8 with mc 68020, 68030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.4.2.4 interrupt cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.2 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.2.1 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.2.2 data transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.2.3 interrupt interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.2.3.1 priority structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2.3.2 interrupt polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2.2.3.3 vectored interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2.2.4 dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.2.5 fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 2.3 hdlc/sdlc serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.3.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.3.2 procedural support (layer-2 functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.3.2.1 full-duplex lapb/lapd operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.3.2.2 half-duplex sdlc-nrm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.3.2.3 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.3.3 sdlc loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 2.3.4 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 2.3.4.1 shared flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 2.3.4.2 preamble transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 2.3.4.3 crc-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 2.3.4.4 extended transparent transmission and reception . . . . . . . . . . . . . . . . . . .69 2.3.4.5 cyclic transmission (fully transparent) . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 2.3.4.6 continuous transmission (dma mode only) . . . . . . . . . . . . . . . . . . . . . . . . .70 2.3.4.7 receive length check feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 2.3.4.8 one bit insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 2.3.4.9 crc on/off feature (version 2 upward) . . . . . . . . . . . . . . . . . . . . . . . . . .71 table of contents page
semiconductor group 5 general information 2.3.4.10 receive address handling (version 2 upward) . . . . . . . . . . . . . . . . . . . . . . .72 2.4 asynchronous serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 2.4.1 character frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 2.4.2 data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 2.4.2.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 2.4.2.2 storage of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 2.4.3 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 2.4.4 special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 2.4.4.1 break detection/generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 2.4.4.2 flow control by xon/xoff (version 2 upward) . . . . . . . . . . . . . . . . . . . . . .75 2.4.4.3 continuous transmission (dma mode only) . . . . . . . . . . . . . . . . . . . . . . . . .77 2.5 character oriented serial mode (monosync/bisync) . . . . . . . . . . . . . . .78 2.5.1 data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 2.5.2 data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 2.5.3 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 2.5.4 special functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 2.5.4.1 preamble transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 2.5.4.2 continuous transmission (dma mode only) . . . . . . . . . . . . . . . . . . . . . . . . .81 2.5.4.3 crc parity inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 2.6 serial interface (layer-1 functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 2.6.1 clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 2.6.2 clock recovery (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 2.6.3 bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 2.6.3.1 bus access procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 2.6.3.2 collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 2.6.3.3 priority (hdlc/sdlc mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.6.3.4 timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.6.3.5 functions of rts output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 2.6.4 data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 2.6.5 modem control functions ( rts/ cts, cd) . . . . . . . . . . . . . . . . . . . . . . . . . .97 2.6.5.1 rts/ cts handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 2.6.5.2 carrier detect (cd) receiver control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 2.6.6 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 2.7 universal port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 3.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 3.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 3.3 operational phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 3.3.1 data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 3.3.1.1 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 3.3.1.2 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 table of contents (contd) page
semiconductor group 6 general information 3.3.2 data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 3.3.2.1 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 3.3.2.2 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 4 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 4.1 status/control registers in hdlc mode . . . . . . . . . . . . . . . . . . . . . . . . . . .112 4.1.1 register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 4.1.2 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 4.2 status/control registers in async mode . . . . . . . . . . . . . . . . . . . . . . . . . .153 4.2.1 register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 4.2.2 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 4.3 status/control registers in bisync mode . . . . . . . . . . . . . . . . . . . . . . . . .188 4.3.1 register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 4.3.2 register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 5 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 5.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 5.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 5.4.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 5.4.1.1 siemens/intel bus interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 5.4.2 parallel port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 5.4.3 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 5.4.3.1 clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 5.4.3.2 receive cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 5.4.3.3 transmit cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 5.4.3.4 strobe timing (clock mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 5.4.3.5 synchronization timing (clock mode 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 5.4.4 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 7 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 table of contents (contd) page
general information semiconductor group 7 introduction the enhanced serial communication controller escc8 (sab 82538) is a data communication device with eight serial channels. it has been designed to implement high-speed communication links and to reduce hardware and software overhead needed for serial synchronous/asynchronous communications. each channel contains an independent clock generator, dpll, encoder/decoder and a programmable protocol part. data communication with asynchronous, synchronous character oriented, and hdlc based protocols with extended support of x.25 0, the isdn 0, and sdlc protocols is implemented. like the dual channel escc2 (sab 82532) the escc8 is capable of handling a large set of layer-2 protocol functions independently of the host processor. the version 82538h-10 of the enhanced serial communication controller (escc8) opens a wide area for applications which use time division multiplex methods (e.g. time- slot oriented pcm systems, systems designed for packet switching, isdn applications) by its programmable telecom-specific features. specifically in one of its timing modes (clock mode 5), which is applicable to all serial modes (hdlc/sdlc, async, bisync), the escc8 can transmit or receive data packets in one of up to 64 time-slots of programmable width. the device is controlled via a parallel 16-bit wide interface which is directly compatible with the most popular 8/16 bit microprocessors (siemens/intel or motorola type). the internal fifos (64 bytes per direction and channel) with additional dma capability provide a powerful interface to the higher layers implemented in a microcontroller. for interrupt controlled systems, the escc8 supports daisy chaining and interrupt vector generation. the escc8 is fabricated using siemens advanced cmos technology and is available in a p-mqfp-160 package. applications l universal, multiprotocol communication boards l asynchronous and synchronous terminal cluster controllers l lan gateways and bridges l multiplexers, cross-connect points, dmi boards l time slotted packet networks l packet switches, packet assemblers/disassemblers
semiconductor group 8 03.95 enhanced serial communication controller sab 82538 (escc8) saf 82538 preliminary data cmos ic 1 general features serial interface l eight independent full duplex serial channels C on chip clock generation or external clock source C on chip dpll for clock recovery of each channel C eight independent baud rate generators C independent time-slot assignment for each channel with programmable time-slot length (1-256 bits) l async., sync. character oriented (monosync / bisync) or hdlc/sdlc modes (including sdlc loop) l transparent receive/transmit of data bytes without framing l nrz, nrzi, fm and manchester encoding l modem control lines ( rts, cts, cd) l crc support: C hdlc/sdlc: crc-ccitt or crc-32 (automatic handling for transmit/receive direction) C bisync: crc-16 or crc-ccitt (support for transmit direction) l support of bus configuration by collision detection and resolution p-mqfp-160 type ordering code package max. data rate clocked time- slot mode ext. int. (dpll) sab 82538 h q67100-h6440 p-mqfp-160 2 mbit/s 2 mbit/s no sab 82538 h-10 q67100-h6441 p-mqfp-160 10 mbit/s 2 mbit/s yes saf 82538 h-10 q67100-h6442 p-mqfp-160 10 mbit/s 2 mbit/s yes
sab 82538 saf 82538 semiconductor group 9 l statistical multiplexing l continuous transmission of 1 to 32 bytes possible l programmable preamble (8 bit) with selectable repetition rate (hdlc/sdlc and bisync) l data rate up to 10 mbit/s l master clock mode with data rate up to 4 mbit/s protocol support (hdlc / sdlc) l various types of protocol support depending on operating mode C auto mode (automatic handling of s and i frames) C non-auto mode C transparent mode l handling of bit oriented functions l support of lapb / lapd / sdlc / hdlc protocol in auto mode (i- and s-frame handling) l modulo 8 or modulo 128 operation l programmable time-out and retry conditions l programmable maximum packet size checking mp interface and ports l 64 byte fifos per channel and direction (byte or word access) l 8/16 bit microprocessor bus interface (intel or motorola type) l all registers directly accessible (byte and word access) l efficient transfer of data blocks from/to system memory via dma or interrupt request l support of daisy chaining and slave operation with interrupt vector generation l 28-bit programmable universal i/os general l advanced cmos technology l low power consumption: active 200 mw at 2 mhz/standby 20 mw (typical values) l p-mqfp-160 package
sab 82538 saf 82538 semiconductor group 10 pin configuration of escc8 (top view) p-mqfp-160
sab 82538 saf 82538 semiconductor group 11 1.1 pin definitions and function note: all unused input pins have to be connected to a defined level pin no. symbol input (i) output (o) function 92 84 a0 a8 i address bus these inputs interface with nine bits of the systems address bus to select one of the internal registers for read or write. 23 30, 33 40 d0 d15 i/o data bus bi-directional three-state data lines which interface with the systems data bus. their configuration is controlled by the level of pin width: C 8-bit mode (width = 0): d0 d7 are active. d8 d15 are in high impedance and have to be connected to v dd or v ss . C 16-bit mode (width = 1): d8d15 are active. in case of byte transfers, the active half of the bus is determined by a0 and bhe/ ble and the selected bus interface mode (via ale). the unused half is in high impedance. for detailed information, refer to chapter 2.2.1 . 97 ale i address latch enable the level at this pin defines the bus interface mode: fixed to 0: demultiplexed siemens/intel bus interface fixed to 1: demultiplexed motorola bus interface switching: multiplexed siemens/intel bus interface the address information provided on lines a0 a8 is internally latched with the falling edge of ale. this function allows the escc8 to be directly connected to a multiplexed address/data bus. in this case, pins a0 a8 must be externally connected to the data bus pins.
sab 82538 saf 82538 semiconductor group 12 pin definitions and function (contd) pin no. symbol input (i) output (o) function 95 rd/ ds i read enable (siemens/intel bus mode) this signal indicates a read operation. when the escc8 is selected via cs the rd signal enables the bus drivers to output data from an internal register addressed via a0 a8 on to data bus. for more information about control/status register and fifo access in the different bus interface modes refer to chapter 2 . if dma transfer is selected via dackx, the rd signal enables the bus drivers to put data from the corresponding receive fifo on the data bus. inputs a1 a8 are ignored. a0 and bhe/ ble are used to select byte or word access. data strobe (motorola bus mode) this pin serves as input to control read/write operations. 96 wr/r/ wi write enable (siemens/intel bus mode) this signal indicates a write operation. when cs is active the escc8 loads an internal register with data provided via the data bus. for more information about control/status register and fifo access in the different bus interface modes refer to chapter 2 . if dma transfer is selected via dackx the wr signal enables latching data from the data bus on the top of the corresponding transmit fifo. inputs a0 a8 are ignored. read/write enable (motorola bus mode) this signal distinguishes between read and write operation. 94 cs i chip select a low signal selects the escc8 for read/write operations. cs has no function in interrupt acknowledge or dma cycles.
sab 82538 saf 82538 semiconductor group 13 pin definitions and function (contd) pin no. symbol input (i) output (o) function 81 res i reset a high signal on this pin forces the escc8 into reset state. during reset the escc8 is in power up mode, after reset in power down mode. re- activation of each channel is done via bit ccr0.pu ( refer to chapter 3.2 ). during reset C all uni-directional output stages are in high- impedance state, C all bi-directional output stages (data bus) are in high-impedance state if signals rd and inta are high, C output xtal2 is in high-impedance if input xtal1 is high (the internal oscillator is disabled during reset) 93 bhe/ ble i bus high enable (siemens/intel bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the upper byte of the data bus (d8 d15). in 8-bit bus interface mode this signal has no function and should be tied to v dd . refer to chapter 2.2.1 for detailed information. bus low enable (motorola bus mode) if 16-bit bus interface mode is enabled, this signal indicates a data transfer on the lower byte of the data bus (d0 d7). in 8-bit bus interface mode this signal has no function and should be tied to v dd . refer to chapter 2.2.1 for detailed information. 82 width i width of bus interface (bus interface mode) a low signal on this input selects the 8-bit bus interface mode. a high signal on this input selects the 16-bit bus interface mode. in this case word transfer to/from the internal registers is enabled. byte transfers are implemented by using a0 and bhe/ ble.
sab 82538 saf 82538 semiconductor group 14 pin definitions and function (contd) pin no. symbol input (i) output (o) function 105 dtack od data transfer acknowledge during a bus cycle (read/write, asynchronous bus), this signal indicates that escc8 is ready for data transfer. the signal remains active until the data strobe ( ds, rd or wr) and/or the chip select signal ( cs) or the interrupt acknowledge ( inta) go inactive. an external resistor has to be tied to v dd if this function is used. 104 int o/od interrupt request int serves as general interrupt request which may include all serial mode specific interrupt sources and the requests of the four universal ports if programmed. these interrupt sources can be masked via registers imr0/1 (for each channel) and pima,b,c,d (universal ports). interrupt status is reported via registers gis (global interrupt status), isr0/1 (for each channel) and pisa,b,c,d (universal ports). output characteristics (push-pull active low/high, open drain) are determined by programming the ipc register. in daisy chain cascading mode int signal generation is only enabled if the interrupt enable input ie1 is active high. int is reset if Cinterrupts are disabled in daisy chain cascading mode (pin ie1 = low), Cno further interrupt is pending, i.e. all interrupt status bits are reset.
sab 82538 saf 82538 semiconductor group 15 pin definitions and function (contd) pin no. symbol input (i) output (o) function 98 inta i interrupt acknowledge if the interrupt is acknowledged via pin inta, an interrupt vector is output on d0d7. all interrupt sources are organized in groups with fixed priority. the priority of the channels within a group is fixed or adjusted dynamically (rotating priority scheme, version 2 upward) ( refer to chapter 2 ). the generated interrupt vector refers to the interrupt group and the requesting channel with currently highest priority (although more than one interrupt source/group may be active). reaction on inta signal depends on the bus interface mode and the cascading mode in conjunction with the interrupt enable pins ie0-2 (ref. to ipc register): motorola bus mode: int is reset with the rising edge of the following valid inta cycle if no further interrupt is pending. the interrupt vector is output with signal ds. siemens/intel bus mode: int is reset with the rising edge of the second valid inta cycle (2-cycle 86 mode) if no further interrupt is pending. slave mode: interrupt acknowledge is accepted if an interrupt signal has been generated and the slave address provided via ie0-2 corresponds to the programmed value (ipc register). daisy chaining mode: interrupt acknowledge is accepted if an interrupt signal has been generated and interrupt enable input ie1 is active during the following inta cycle. note: pins cs, dackx have to be inactive during an inta cycle. if pin inta is not used, it has to be tied to v dd .
sab 82538 saf 82538 semiconductor group 16 pin definitions and function (contd) pin no. symbol input (i) output (o) function 101 100 99 ie0 ie1 ie2 i/o i i interrupt enable 0, 1, 2 the function depends on the selected cascading mode: slave mode: ie0-2 are inputs. interrupt acknowledge is accepted if an interrupt signal has been generated and the slave address provided via ie0, ie1, ie2 corresponds to the programmed value (ipc register). if not used, ie0-2 should be tied to gnd and the slave address should be set to 0 (e.g. single device application). daisy chaining mode: ie0 is output, ie1 is input. ie2 is unused and has to be fixed to 0 or 1. normally, ie1 is connected to the ie0 pin of devices with higher priority. if not used, ie1 has to be fixed to 1. if ie1 is reset (0) C the ie0 output is reset immediately, C an active int signal will be prohibited or aborted. C int is hold inactive unconditionally as long as ie1 is 0. as long as inta input is inactive, ie1 = 1 enables int signal generation. if int goes active, pin ie0 immediately is set to 0. interrupt acknowledge is accepted if the interrupt enable input ie1 is active during the following inta cycle. during this cycle, and additionally till the end of the second inta cycle in siemens/intel bus mode, triggering of int signal generation is prohibited, i.e. no interrupt will be generated while (another) device is under service. this is valid even for devices with higher priority. pin ie0 returns to active state (logical 1) when int is deactivated and ie1 input is high.
sab 82538 saf 82538 semiconductor group 17 pin definitions and function (contd) pin no. symbol input (i) output (o) function 1 2 3 4 5 6 7 8 drt0 drt1 drt2 drt3 drt4 drt5 drt6 drt7 o dma request transmitter (channel 0 ... 7) the transmitter on a serial channel requests a dma transfer by activating the corresponding drt line. the request remains active as long as the corresponding transmit fifo requires data transfers. the amount of data bytes to be transferred from the system memory to the escc8 serial channel (= byte count) must be written first to the xbch, xbcl registers. always blocks of data (n x 32 bytes + rest, n = 0, 1,) are transferred till the byte count is reached. drtn is deactivated with the beginning of the last write cycle. 160 159 158 157 156 155 154 153 drr0 drr1 drr2 drr3 drr4 drr5 drr6 drr7 o dma request receiver (channel 0 7) the receiver on a serial channel requests a dma transfer by activating the corresponding drt line. the request remains active as long as the corresponding receive fifo requires data transfers, thus always blocks of data are transferred. drrn is deactivated immediately following the falling edge of the last read cycle.
sab 82538 saf 82538 semiconductor group 18 pin definitions and function (contd) pin no. symbol input (i) output (o) function 73 74 75 76 77 78 79 80 dack0 dack1 dack2 dack3 dack4 dack5 dack6 dack7 i dma acknowledge (channel 0 7) a low signal on these pins informs the escc8 that the requested dma cycle controlled via drt or drr of the corresponding channel is in progress, i.e. the dma controller has achieved bus mastership from the cpu and will start data transfer cycles (either write or read). in conjunction with a read or write operation these inputs serve as access enable (similar to cs) to the respective fifos. if dack is active, the input to pins a1a8 is ignored and the fifos are implicitly selected. a0 and bhe/ ble are used to select byte or word access. if not used, these pins must be connected to v dd . 14 16 20 22 112 110 108 106 rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 i (o/od) receive data (channel 0 7) serial data is received on these pins. may be switched to t d function via bit ccr2.soc1. 49 50 51 52 69 70 71 72 rxclk0 rxclk1 rxclk2 rxclk3 rxclk4 rxclk5 rxclk6 rxclk7 i receive clock (channel 0 7) the function of these pins depends on the selected clock mode. in each channel, r clkn may supply either C the receive clock (clock mode 0), or C the receive and transmit clock (clock mode 1, 5), or C the clock input for the baud rate generator (clock mode 2, 3).
sab 82538 saf 82538 semiconductor group 19 pin definitions and function (contd) pin no. symbol input (i) output (o) function 41 42 43 44 45 46 47 48 rts0 rts1 rts2 rts3 rts4 rts5 rts6 rts7 o request to send (channel 0 7) when the rts bit in the mode register is set, the rts signal goes low. when the rts bit is reset, the signal goes high if the transmitter has finished and there is no further request for a transmission. in bus configuration, rts can be programmed via ccr2 to: C go low during the actual transmission of a frame shifted by one clock period, excluding collision bits. C go low during reception of a data frame. C stay always high ( rts disabled). 134 133 132 131 130 129 128 127 cts0/cxd0 cts1/cxd1 cts2/cxd2 cts3/cxd3 cts4/cxd4 cts5/cxd5 cts6/cxd6 cts7/cxd7 i clear to send (channel 0 7) a low on the ctsn input enables the respective transmitter. additionally, an interrupt may be issued if a state transition occurs at the ctsn pin (programmable feature). if no clear to send function is required, the ctsn inputs can be directly connected to gnd. collision data (channel 0 7) in a bus configuration, the external serial bus must be connected to the corresponding c d pin for collision detection. 126 125 124 123 122 121 120 119 cd0 cd1 cd2 cd3 cd4 cd5 cd6 cd7 i carrier detect (channel 0 7) the function of this pin depends on the selected clock mode. it can supply: C either a modem control or a general purpose input (clock modes 0,2,3,4,6,7). if auto-start is programmed, it functions as a receiver enable signal. C or a receive strobe signal (clockmode 1). C or a frame synchronization signal in time-slot oriented operation mode (clock mode 5). additionally, an interrupt may be issued if a state transition occurs at the cdn pin (programmable feature).
sab 82538 saf 82538 semiconductor group 20 pin definitions and function (contd) pin no. symbol input (i) output (o) function 13 15 19 21 113 111 109 107 txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 o/od transmit data (channel 0 7) transmit data is shifted out via these pins. they can be programmed to be either a push-pull or open drain output to support bus configurations. note: pin txd is or ed with pin rts if nrzi encoding and idle as interframe time fill are selected and bit mode.rts is reset. may be switched to rxd function via bit ccr2.soc1. 9 10 11 12 118 117 116 115 txclk0 txclk1 txclk2 txclk3 txclk4 txclk5 txclk6 txclk7 i/o transmit clock (channel 0 7) the function of this pin depends on the selected clock mode and the value of the ssel bit (ccr2 register). for detailed information about the clock modes refer to chapter 2 . if programmed as an input, this pin supplies either C the transmit clock for the channel (clock mode 0, 2, 6; ssel bit in ccr2 is reset), or C a transmit strobe signal for the channel (clock mode 1). if programmed as an output (bit ccr2.toe is set), this pin supplies either C the transmit clock for the channel which is generated l either from the baud rate generator (clock mode 2, 3, 6, 7; ssel bit in ccr2 is set), l or from the dpll circuit (clock mode 3, 7; ssel bit in ccr2 is reset) l or from the crystal oscillator (clock mode 4), l or an active-low tri-state control signal marking the programmed transmit time-slot (clock mode 5) if bit ccr2.toe is set.
sab 82538 saf 82538 semiconductor group 21 pin definitions and function (contd) pin no. symbol input (i) output (o) function 63 64 xtal1 xtal2 i (o) crystal connection if the internal oscillator is used for clock generation the external crystal has to be connected to these pins. moreover, xtal1 may be used as common clock input for all channels provided by an external clock generator. all versions: common use for both channels in clock modes 4,6,7. version 2 upward: additionally used in clock mode 0b and for master clock applications. 152 ? 145 53 ? 60 142 ? 135 65 ? 68 pa0 7 pb0 7 pc0 7 pd0 3 i/o parallel port (port a,b,c,d) four general purpose bi-directional parallel ports (port a,b,c: 8 bit; port d: 4 bit). every pin is individually programmable to operate as an output or an input (port configuration register pcra,b,c,d). C if defined as output, the state of the pin is directly controlled via the microprocessor interface(portvalueregister pvra,b,c,d) C if defined as input, its state can be read via pvra,b,c,d. all changes may be indicated via an interrupt status (port interrupt mask register pima,b,c,d, port interrupt status register pisa,b,c,d, interrupt is output on pin int). 18, 32, 61, 102, 114, 143 v ss i ground (0 v) for correct operation, all six pins have to be connected to ground. 17, 31, 62, 103, 144 v dd i positive power supply (5 v) for correct operation, all five pins have to be connected to positive power supply. 83 test i test input this pin always has to be connected to v ss . (test input for the manufacturer)
sab 82538 saf 82538 semiconductor group 22 1.2 logic symbol figure 1 escc8 logic symbol
sab 82538 saf 82538 semiconductor group 23 1.3 functional block diagram figure 2 functional block diagram sab 82538
sab 82538 saf 82538 semiconductor group 24 the escc8 (sab 82538) comprises eight completely independent full-duplex serial interfaces which support hdlc/sdlc, bisync and async protocols. layer-1 functions are performed by means of internal oscillator, baud rate generator (brg), digital phase locked loop (dpll), and time-slot assignment circuits (tsa, only available for version sab 82538h-10). encoding / decoding of serial data can be done by using nrz, nrzi, fm0, fm1, and manchester encoding schemes. an 28-bit universal port is provided which can be used for additional modem control lines or for general i/o purposes. associated with each serial channel is a set of independent command and status registers and 64-byte deep fifos for transmit and receive direction. access is done via the flexible 8/16-bit microprocessor interface. dma capability has been added to the escc8 by means of a 16-channel dma interface with one dma request line for each transmitter and receiver of both channels. the interrupt structure of escc8 supports interrupt driven systems using interrupt polling, daisy chaining or interrupt vector control.
sab 82538 saf 82538 semiconductor group 25 1.4 system integration 1.4.1 general aspects figure 3 general system integration of escc8 figure 3 gives a general overview of system integration of escc8. the escc8s bus interface consists of an 8/16-bit bidirectional data bus (d0-d15), nine address line inputs (a0-a8), three control inputs ( rd / ds, wr / r/ w, cs), five signals for interrupt support (int, inta, ie0-2) and a 16-channel dma interface. mode input pins (strapping options) allow the bus interface to be configured for 8/16-bit bus width and for either siemens/intel or motorola environment. generally, there are two types of transfers occurring via the system bus: C command/status transfers, which are always controlled by the cpu. the cpu sets the operation mode (initialization), controls function sequences and gets status information by writing or reading the escc8s registers (via cs, wr or rd, and register address via a0-a8, bhe). C data transfers, which are effectively performed by dma without cpu interaction using the escc8s dma interface (dma mode). optionally, interrupt controlled data transfer can be done by the cpu (interrupt mode).
sab 82538 saf 82538 semiconductor group 26 1.4.2 environment 1.4.2.1 escc8 with sab 80188 microprocessor a system with minimized additional hardware expense can be build up with a sab 80188 microprocessor as shown in figure 4 . figure 4 escc8 with sab 80188 cpu the escc8 is connected to the demultiplexed system bus. data transfer for one serial channel can be done by the 2-channel on-chip dma controller of the 80188, the other channels are serviced by interrupt. since the 80188 does not provide dma acknowledge outputs, data transfer from/to escc8 is controlled via cs, rd or wr address information (a1 a8) and the dack0-7 inputs are not used. a0 and bhe/ ble are used to select byte or word access.
sab 82538 saf 82538 semiconductor group 27 this solution supports applications with a high speed data rate in one serial channel with minimum hardware expense making use of the on-chip peripheral functions of the 80188 (chip select logic, interrupt controller, dma controller). 1.4.2.2 escc8 with 80386 in high-performance 32-bit systems based on an 80386 microprocessor a separate control logic (e.g. sequencer pals) is normally provided to generate all necessary control signals for interfacing to i/o devices. address and data lines are buffered via latches or transceivers. an interface to escc8 is for this case sketched in figure 5 . figure 5 escc8 with 80386 m p
sab 82538 saf 82538 semiconductor group 28 1.4.2.3 escc8 with mc 68020, 68030 figure 6 gives an example of interfacing the escc8 to a 32-bit motorola microprocessor. some glue logic is necessary. the signal bus low enable (ble) has to be decoded out of transfer size information (siz0,1) and a0. the escc8 interface logic has to respond as a 16-bit peripheral (dsack1,0 = 01 h ) during register access and interrupt acknowledge cycles. figure 6 escc8 with 68020 m p
sab 82538 saf 82538 semiconductor group 29 1.4.2.4 interrupt cascading the escc8 supports two cascading schemes which can be selected by programming the ipc register: slave mode interrupt outputs of several devices (slaves) are connected to a priority resolving unit (e.g. interrupt controller). the slave which is selected for the interrupt service routine is addressed via special address lines during the interrupt acknowledge cycle. for this application the escc8 offers three interrupt enable inputs (ie0, ie1,ie2) and a programmable 3-bit slave id. figure 7 interrupt cascading (slave mode) in intel bus mode for intel type microprocessor systems the 2-cycle interrupt acknowledge scheme is supported (86 mode).
sab 82538 saf 82538 semiconductor group 30 figure 8 interrupt cascading (slave mode) in motorola bus mode
sab 82538 saf 82538 semiconductor group 31 daisy chaining if selected via ipc register the interrupt enable pins ie0, ie1 are used for building a daisy chain by connecting the interrupt enable output (ie0) of the higher priority device to the interrupt enable input (ie1) of the lower priority device. the highest priority device has ie1 pulled high ( refer to figure 9 and 10 ). ie2 is unused and has to be fixed to 0 or 1. figure 9 interrupt cascading (daisy chaining) in intel bus mode for intel type microprocessor systems the 2-cycle interrupt acknowledge scheme is supported (86 mode). maximum available settling time for the chain: from the beginning of the first inta cycle to the beginning of the second.
sab 82538 saf 82538 semiconductor group 32 figure 10 interrupt cascading (daisy chaining) in motorola bus mode for motorola type microprocessor systems the maximum available settling time for the chain is much shorter: from the beginning of the inta cycle to the falling edge of signal ds.
sab 82538 saf 82538 semiconductor group 33 2 functional description 2.1 general the escc8 distinguishes itself from other communication controllers by its advanced characteristics. the most important are: l eight independent serial channels. l support of hdlc, sdlc, bisync/monosync and asynchronous protocols. l support of layer-2 functions (hdlc mode). in addition to those bit-oriented functions commonly supported by hdlc controllers, such as bit stuffing, crc check, flag and address recognition, the escc8 provides a high degree of procedural support. in a special operating mode (auto-mode), the escc8 processes the information transfer and the procedure handshaking (i- and s-frames of hdlc protocol) autonomously. the only restriction is that the window size (= number of outstanding unacknowledged frames) is limited to 1, which is sufficient for many applications. the communication procedures are mainly processed between the communication controllers and not between the attached processors. thus the dynamic load on the cpu and the software expense is greatly reduced. the cpu is informed about the status of the procedure and has mainly to manage the receive and transmit data. in order to maintain cost effectiveness and flexibility, the handling of unnumbered (u) frames, and special functions such as error recovery in case of protocol errors, are not implemented in hardware and must be done by the users software. l extended support of different link configurations. besides the point-to-point configurations, the escc8 allows the implementation of point-to-multipoint or multi-master configurations without additional hardware or software expense. in point-to-multipoint configurations, the escc8 can be used as a master or as a slave station. even when working as slave station, the escc8 can initiate the transmission of data at any time. an internal function block provides means of idle and collision detection and collision resolution, which are necessary if several stations start transmitting simultaneously. thus, a multi-master configuration is also possible. l telecom specific features. in a special operating mode, the escc8 can transmit or receive data packets in one of up to 64 time-slots of programmable width (clock mode 5). furthermore, the escc8 can transmit or receive variable data portions within a defined window of one or more clock cycles in conjunction with an external strobe signal (clock mode 1). these features make the escc8 suitable for applications using time division multiplex methods, such as time-slot oriented pcm systems or systems designed for packet switching.
sab 82538 saf 82538 semiconductor group 34 l fifo buffers for efficient transfer of data packets. a further speciality of escc8 are the 64-byte deep fifo buffers used for the temporary storage of data packets transferred between the serial communications interface and the parallel system bus. because of the overlapping input/output operation (dual-port behaviour), the maximum message length is not limited by the size of the buffer. the dynamic load of the cpu is drastically reduced by transferring the data packets block by block via direct memory access supported by the escc8. the cpu only has to initiate the data transmission by the escc8 and determine the status in case of completed reception, but is not involved in data transfers. l the 16-bit wide microprocessor interface enables high data throughput and offers a high flexibility for connection to both 8/16-bit siemens/intel and motorola type microprocessor systems. moreover, interrupt driven systems are supported by vectored interrupts and interrupt cascading capabilities. l in addition to standard modem control lines associated with each of the serial channels, 28 universal ports are provided for applications related to or independent of the serial channels.
sab 82538 saf 82538 semiconductor group 35 link configurations figure 11 point-to-point configuration figure 12 point-to-multipoint configuration figure 13 multimaster configuration
sab 82538 saf 82538 semiconductor group 36 2.2 microprocessor interface 2.2.1 register set the communication between the cpu and the escc8 is done via a set of directly accessible registers. the interface may be configured as siemens/intel or motorola type with a selectable data bus width of 8 or 16 bits. the cpu transfers data to/from the escc8 (via 64 byte deep fifos per direction and channel), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. all accesses can be done as byte or word accesses if enabled. if 16-bit bus width is selected, access to lower/upper part of the data bus is determined by address line a0 and signal bhe/ ble as shown in table 1 and 2 . mixed byte/word access to the fifos reading from or writing to the internal fifos (rfifo and xfifo of each channel) can be done using a 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. in version 1 of escc8, byte access in the case of 16-bit bus interface mode is allowed if not mixed with word accesses when reading from or writing to the same pool. in version 2.x and upwards randomly mixed byte/word access to the fifos is allowed without any restrictions. table 1 data bus access (16-bit intel mode) bhe a0 register access escc8 data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d8 C d15 1 0 register byte access (even addresses) d0 C d7 1 1 no transfer performed none
sab 82538 saf 82538 semiconductor group 37 table 2 data bus access (16-bit motorola mode) the assignment of registers with even/odd addresses to the data lines in case of 16-bit register access depends on the selected microprocessor interface mode: siemens/intel (adr. n + 1) (adr. n) motorola (adr. n) (adr. n + 1) -- n: even address complete information concerning register functions is provided in chapter 4 C detailed register description. the most important functions programmable via these registers are: l setting of serial, operating and clocking modes l layer-2 functions l data transfer modes (interrupt, dma) l bus mode l dpll mode l baud rate generator l test loop. each of the eight serial channels of escc8 is controlled via an identical, but totally independent register set (channel 07). functions which are common to or independent from all eight channels, e.g. interrupt information or universal port programming, are accessible via all register sets, which simplifies software development. ble a0 register access escc8 data pins used 0 0 fifo word access register word access (even addresses) d0 C d15 0 1 register byte access (odd addresses) d0 C d7 1 0 register byte access (even addresses) d8 C d15 1 1 no transfer performed none data lines d15 d8 d7 d0
sab 82538 saf 82538 semiconductor group 38 2.2.2 data transfer modes data transfer between the system memory and the escc8 for all eight channels is controlled by either interrupts (interrupt mode), or independently from cpu, using the escc8's 16-channel dma interface (dma mode). after reset, the escc8 operates in interrupt mode, where data transfer must be done by the cpu. the user selects the dma mode by setting the dma bit in the xbch register. all eight channels can be independently operated in either interrupt or dma mode. 2.2.3 interrupt interface special events in the escc8 are indicated by means of a single interrupt output with programmable characteristics (open drain, push-pull; ipc register), which requests the cpu to read status information from the escc8, or, if interrupt mode is selected, to transfer data from/to escc8. since only one int request output is provided, the cause of an interrupt must be determined by the cpu l by evaluating the interrupt vector which is generated by escc8 during an interrupt acknowledge cycle ( note : for version 2 upward the format of the interrupt vector is changed to separate parallel port interrupts from channel assigned interrupts), and/or l by reading the escc8's interrupt status registers (gis, isr0, isr1, pis).
sab 82538 saf 82538 semiconductor group 39 the structure of the interrupt status registers is shown in figure 14 . figure 14 escc8 interrupt status registers each interrupt indication of registers isr0, isr1 and pis can be selectively masked by setting the corresponding bit in the corresponding mask registers imr0, imr1 and pim. use of these registers depends on the selected serial mode. gis, the non-maskable global interrupt status register serves as pointer to pending channel related interrupts and universal port interrupts. 2.2.3.1 priority structure the escc8 has a two level priority structure with different classifications ( refer to figure 15 ): first level: type classification all types of interrupt sources are divided into four groups with fixed priority levels. group 0 (highest priority): includes the receive pool full interrupts of all channels. group 3 (lowest priority): refers to all other interrupt sources of all channels except those of group 0...2. examples: timer interrupt, transmit fifo overflow interrupt,
sab 82538 saf 82538 semiconductor group 40 second level: channel classification the second level considers the current priority of all channels. especially for version 2 upward, selection is performed between C fixed priority level assignment (version 1: channel 0 has highest and channel 7 lowest priority; version 2 upward: channel with highest priority is selectable) C rotating priority level assignment, all channels (version 2 upward) C rotating priority level assignment, 7 channels with the selectable 8th channel fixed to highest priority (version 2 upward) the priority level for each interrupt source results from the interrupt group (first level) and the current priority of the channel (second level). as mentioned above, in escc8 version 1 the priorities of the eight serial channel interrupts are fixed, with channel 0 having always the highest, channel 7 the lowest priority. for escc8 version 2 upward the priority levels are fixed or adjusted after an interrupt has been serviced, namely, the priorities are rotated cyclically so that the channel last serviced is assigned the lowest priority of all. port interrupts are not affected by the priority rotation, and are always assigned lowest priority. the interrupt priority rotation mode is selectable via two control bits iva.rot and ipc.rotm. when an interrupt has been generated updating of all interrupt priorities takes place after the generated interrupt has been acknowledged, i.e. C for interrupts that are unambiguously determined by the contents of the interrupt vector, after the end of a complete intaq cycle (1 or 2 pulse, whichever applies). such interrupts are: receive data interrupts rpf, rme/tcd and transmit data interrupt xpr for all channels, or, C whenever the interrupt status which caused the currently active interrupt to be generated (i.e. one with currently the highest priority among all unmasked pending interrupts) is cleared by reading an interrupt status register isr0_0...7, isr1_0...7 or pisa...d. reading other interrupt status registers may clear other pending interrupts (if any). the following interrupt priority modes apply only to the channel identification (second level). interrupt priority mode 1: fixed priority after reset the escc8 operates with fixed priority, i.e. the relative order of the priority levels assigned to the channels is fixed and there is no change after an interrupt has been serviced. apart from the change in the format of the interrupt vector (version 2 upward: channel 7 interrupts are separated from the parallel ports interrupts) version 2 is compatible with
sab 82538 saf 82538 semiconductor group 41 version 1 if the optional features of version 2 are not enabled: channel 0 has highest and channel 7 lowest (channel) priority. note: parallel ports have always lowest priority. version 2 upward provides dynamic adjustment of channel priorities by programming the highest priority channel. this is done via the iva register. although this register is unique, it is accessible via all eight channel assigned addresses. selection of the highest priority channel is simply done with every write access to the iva register in conjunction with the channel assigned iva register address: iva register address: highest priority channel 38 h 0 78 h 1 b8 h 2 f8 h 3 138 h 4 178 h 5 1b8 h 6 1f8 h 7 the priority level becomes valid with the end of the write access to the iva register (rising edge of wr or ds, whichever applies) and remains stable until a new write access to this register occurs. note: C the sequence of the channels remains unchanged. only the pointer to the channel with highest priority is influenced. therefore, the priority levels of all other channels follow automatically. C parallel ports have always lowest priority. if the state after reset shall be unchanged but bits of the iva register have to be set, the programming has to be done via iva register address 38h (channel 0). example: initially after reset, the order of the channels with descending priority from left to right is as follows: 0 1 2 3 4 5 6 7 pp (pp = parallel port interrupt) supposed the iva register is programmed via the address 138 h (channel 4) the channel priorities will be reordered as follows: 4567 0123 pp
sab 82538 saf 82538 semiconductor group 42 interrupt priority mode 2: rotating priority of 8 channels with iva.rot = 1 and ipc.rotm = 0 the interrupt priority rotation mode is selected. after an interrupt has been serviced the priorities of all eight channels are rotated cyclically so that the channel last serviced is assigned the lowest priority of all. the escc8 will adjust the priorities according to the following scheme. example: suppose the order of the channels is as follows with descending priority from left to right: 0 1 2 3 4 5 6 7 pp (pp = parallel port interrupt) suppose channel 4 requires interrupt service and no other channel / interrupt group with higher priority is or becomes active, so that channel 4 has the currently highest priority of all channels at the time when the interrupt vector is output. after the interrupt in question has been acknowledged, an automatic reordering of the channels (and of pending interrupts, if any) takes place so that channel 4 is given the lowest channel priority. the relative ordering of the channels remains the same: 5670 1234 pp this interrupt priority rotation guarantees fair treatment of all the channels. a reordering of the interrupts takes also place when any other channel interrupt is acknowledged by reading a corresponding interrupt status register, so that the corresponding channel is put behind the others. note: parallel ports have always lowest priority.
sab 82538 saf 82538 semiconductor group 43 interrupt priority mode 3: rotating priority of 7 channels with iva.rot = 1 and ipc.rotm = 1 the priority adjustment is performed only on 7 channels while one channel is fixed to the highest priority level. as described in interrupt priority mode 1 for fixed priority scheme, selection of the highest priority channel is simply done with every write access to the iva register in conjunction with the channel assigned iva register address: iva register address: highest priority channel 38 h 0 78 h 1 b8 h 2 f8 h 3 138 h 4 178 h 5 1b8 h 6 1f8 h 7 if the highest priority channel generates an interrupt and gets serviced by reading the interrupt vector or the interrupt status register of that channel a reordering of the other channels will not take place. the dynamic adjustment of the channel priorities does not affect the interrupt group of an interrupt even if it is the highest priority channel. example: let the channel priorities be labeled as follows with channel 2 as fixed highest priority channel: 2567 0134 pp in descending order. supposing the channel labeled 7 generates an interrupt which is serviced because no unmasked higher priority is pending, the channels will be reordered as follows: 2013 4567 pp even if the same channel generates another interrupt, it will not be serviced before at least one other channel (if any) requesting service by that time. if the channel labeled 2 now generates an interrupt which gets serviced the order is to be the same as above: 2013 4567 pp note: parallel ports have always lowest priority.
sab 82538 saf 82538 semiconductor group 44 figure 15 structure of interrupt vector note: for iva.eda = 1 the interrupt vector format for version 2 is identical to version 1.
sab 82538 saf 82538 semiconductor group 45 2.2.3.2 interrupt polling after escc8 has requested an interrupt by activating its int pin, the cpu must first read the global interrupt status register gis to identify parallel port and/or channel related interrupt indications: l channel related interrupts are indicated via bit gis.cii (channel interrupt indication) and the number of the requesting channel (gis.cn2..0). after reading the assigned interrupt status registers isr0_x and isr1_x, the pointer in register gis is cleared or updated if another channel requires interrupt service. l the 28-bit universal port is divided into four groups (port a,b,c: 8 lines each, port d: 4 lines) which all have the same lowest interrupt priority. pending interrupts are pointed out directly via gis.pia..d. reading the assigned interrupt status registers (pisa..d) will reset the corresponding indication in gis. if all pending interrupts are acknowledged (gis is reset), pin int goes inactive. 2.2.3.3 vectored interrupt structure after escc8 has requested an interrupt by activating its int pin, the system (cpu or peripherals) starts the interrupt acknowledge cycle by activating the inta signal. if the intel bus interface mode is selected, the two-pulse86 mode is supported. in motorola interface mode single pulse acknowledgement is implemented. interrupt acknowledge operation is determined by the selected interrupt cascading mode (ipc register) in conjunction with the interrupt enable signals ie0, ie1 and ie2: l slave mode the address of the slave under service has to be provided via inputs ie0, ie1 and ie2 during the valid inta cycle. interrupt acknowledge is accepted if this address corresponds to the programmed value (ipc register). if the escc8 is used in single device applications (no other device is present for interrupt cascading), ie0..2 have to be fixed to a defined level corresponding to the internally programmed address. l daisy chaining mode ie0 as interrupt enable output and ie1 as interrupt enable input are used to build a daisy chain ( refer to chapter 1.4 ). input ie2 is not used and has to be tied to v ss . interrupt acknowledge is accepted if ie1 is active during the valid inta cycle. output ie0 follows the ie1 input. additionally, ie0 is reset when int goes active. activation of pin int is prohibited C during inta cycles C between the first and the second inta cycle if siemens/intel mode is selected. if interrupt acknowledge is accepted in one of the above modes, the escc8 generates an interrupt vector which is output on d0-d7 of the data bus independent of the selected bus interface mode ( refer to figure 15 ).
sab 82538 saf 82538 semiconductor group 46 implementation of the interrupt service routines should consider the two selectable interrupt vector modes (bit iva.eda): l interrupt vector mode 1 (eda = 0) interrupt vector includes: device address, version 2: parallel port indication, channel identification, interrupt group (+): fastest interrupt source identification (especially for interrupt groups 0..2). (C): interrupt vector table needs 32 (version 2: 64) entry points, placement of this entry field only in steps of 128 bytes (version 1: 3-bit device address; version 2: 2-bit device address), fastest service requires implementation of up to 32 (64) interrupt service routines. in case more than one source is active, the generated vector refers to the interrupt group with highest priority, and within a group to the requesting channel with highest priority. although universal port interrupts and their indications via register gis are independent from channel assigned interrupts, a vector with group 3, channel 7 indication may additionally refer to pending universal port interrupts. in version 2 upward the pi-bit of the interrupt vector indicates a pending parallel port interrupt. interrupt groups 0 to 2 are assigned to definite single interrupt indications per channel. these are urgent receive and transmit interrupts which need to be serviced quickly. due to this, no read access to interrupt status registers is necessary: the corresponding interrupt indication is reset after the inta cycle has been finished. interrupt group 3 combines all other interrupt sources. thus, the interrupt status registers isr0_x and isr1_x which correspond to the requesting channel have to be examined. version 1: if channel 7 is indicated, the global status register gis has to be evaluated for pending channel and/or universal port interrupts. version 2 upward: the pi-bit indicates a pending parallel port interrupt separately from channel 7 interrupts. the int signal is reset when all interrupt indications are cleared (acknowledged). see also exceptions in daisy chaining mode. l interrupt vector mode 2 (eda = 1) interrupt vector includes: extended device address, interrupt group (+): interrupt vector table needs only 4 entry points, placement of this entry field in steps of 16 bytes (6-bit device address), only 4 different interrupt service routines necessary. (C): context switching for each channel necessary (via register gis). in case more than one source is active, the generated vector refers to the interrupt group with highest priority. for identification of the requesting channel, register gis has to be read. bits cn2..cn0 (channel number) have to be used for context switching, i.e. for computing the pointer to channel assigned data structures. note: universal port interrupts indications in register gis are independent of channel assigned interrupts. thus, one of indications pia..d may be set although the generated interrupt vector refers to a group with priority and/or the channel number is less than 7.
sab 82538 saf 82538 semiconductor group 47 subsequent actions depend on the indicated interrupt group (similar to vector mode 1): if one of interrupt groups 0 to 2 is indicated, no reading of channel assigned interrupt status registers is necessary; the corresponding interrupt indication is reset after the inta cycle has been finished. if interrupt group 3 is indicated, the interrupt status registers isr0_x and isr1_x which correspond to the requesting channel have to be examined. version 1: in case channel 7 is indicated the global status register gis has to be evaluated for pending channel and/or universal port interrupts. version 2 upward: the pi-bit indicates a pending parallel port interrupt separately from channel 7 interrupts. the int signal is reset when all interrupt indications are cleared (acknowledged). see also exceptions in daisy chaining mode. note: contents of global interrupt status register gis are frozen after every interrupt acknowledge cycle. updating starts C after the first read access to gis after the interrupt vector has been output, C after every read access to anyone of the channel assigned interrupt status registers, C during every inta cycle. updating of channel assigned interrupt status registers isr0_x and isr1_x is only prohibited during read access. thus, status information may include indications of higher priority even in case of group 3 interrupts (e.g. a timer interrupt tin channel 5 triggers an interrupt vector generation with group 3, channel 5 indication; before the service routine is able to read isr0_5 and isr1_5, an rpf condition occurs for channel 5; the current status information now includes tin and rpf indication). this is implemented to avoid wasting time with servicing of low level requests while an urgent request of that channel is pending. this must be taken into consideration when designing the interrupt service routine for group 3 interrupts. masked interrupts visible in status registers (version 2 upward) the interrupt vector contains only one interrupt at a time: the interrupt displayed in this vector results from a priority resolution among all unmasked active interrupt statuses. the global interrupt status register (gis) points to interrupt status registers with active interrupt indications. register gis should be evaluated if a pure interrupt polling scheme is used. in version 1 of escc8 only unmasked interrupt statuses may: C generate an interrupt at pin int, C generate an interrupt vector, C be visible in gis, and C be visible in the interrupt status registers isr0_0..7, isr1_0..7 and pisa..d.
sab 82538 saf 82538 semiconductor group 48 masked interrupt statuses are only stored internally and they become visible when the mask is withdrawn. in version 2 upward, an additional mode can be selected via bit ipc.vis. in this mode, masked interrupt status bits still neither generate an interrupt at pin int nor generate an interrupt vector nor are visible in gis, but are displayed in the respective interrupt status register(s) isr0_0..7, isr1_0..7 and pisa..d. this mode is useful when some interrupt status bits are to generate an interrupt vector and other status bits are to be polled in the individual interrupt status registers. notes: l in the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. l all unmasked interrupt statuses are treated as before. l please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no hierarchical polling possible), since gis only contains information on actually generated - i.e. unmasked-interrupts.
sab 82538 saf 82538 semiconductor group 49 2.2.4 dma interface the escc8 comprises a 16-channel dma interface for fast and efficient data transfers. for all serial channels, a separate dma request output for transmit (drt) and receive direction (drr) as well as a dma acknowledgement ( dack) input is provided. the escc8 activates the dma request line as long as data transfers are needed from/ to the specific fifo (level triggered demand transfer mode of dma controller). it is the responsibility of the dma controller to perform the correct amount of bus cycles. either read cycles will be performed if the dma transfer has been requested from the receiver, or write cycles if dma has been requested from the transmitter. if the dma controller provides a dma acknowledge signal (input to the escc8s dack pin), each bus cycle implicitly selects the top of the specific fifo and neither address (via a1-a8) nor chip select need to be supplied (i/o to memory transfers). if no dack signal is supplied, normal read/write operations (with addresses) must be performed (memory to memory transfers). the escc8 deactivates the dma request line immediately after the last read/write cycle of the data transfer has started. as a very useful feature for single cycle dma transfers, optional inversion of the functions of read/write control lines is implemented. if programmed via register ccr2 C rd and wr are exchanged in intel bus interface mode, Cr/ w is inverted in motorola bus interface mode while dack is active. this allows easy connection to dma controllers without dedicated i/o control lines as shown in figure 16 . figure 16 dma interfacing by using invert mode
sab 82538 saf 82538 semiconductor group 50 2.2.5 fifo structure in all transmit and receive direction 64-byte deep fifos are provided for the intermediate storage of data between the serial interface and the cpu interface. the fifos are divided into two halves of 32-bytes. only one half is accessible to the cpu or dma controller at any time. organization of the fifos and access to their contents depends on the selected serial mode. for detailed information, refer to description of rfifo and xfifo in chapter 4.1, chapter 4.2 and chapter 4.3 . in case 16-bit data bus width is selected by fixing pin width to logical 1 word access to the fifos is enabled. data output to bus lines d0- d15 as a function of the selected interface mode is shown in figure 17 and 18. of course, byte access is also allowed. the effective length of the accessible part of rfifo can be changed from 32 bytes (reset value) down to 1 (async and bisync mode) or 2 (hdlc mode) bytes. in version 1, only threshold 32 is available in hdlc mode. figure 17 fifo word access (intel mode)
sab 82538 saf 82538 semiconductor group 51 figure 18 fifo word access (motorola mode)
sab 82538 saf 82538 semiconductor group 52 2.3 hdlc/sdlc serial mode 2.3.1 operating modes the hdlc controller of each channel can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be performed in a very flexible way, to satisfy almost any practical requirements. there are 6 different operating modes which can be set via the mode register. auto-mode (mode: mds1, mds0 = 00) characteristics: window size 1, random message length, address recognition. the escc8 processes autonomously all numbered frames (s-, i-frames) of an hdlc protocol. the hdlc control field, data in the i-field of the frames and an additional status byte are temporarily stored in the rfifo. the hdlc control field as well as additional information can also be read from special registers (rhcr, rsta). depending on the selected address mode, the escc8 can perform a 2-byte or 1-byte address recognition. if a 2-byte address field is selected, the high address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. according to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/ response bit (c/r), dependent on the setting of the cri bit in rah1, and will be excluded from the address comparison. similarly, two comparison values can be programmed in special registers (ral1, ral2) for the low address byte. a valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. thus, the escc8 can be called (addressed) with 6 different address combinations, however, only the logical connection identified through the address combination rah1, ral1 will be processed in the auto-mode, all others in the non auto-mode. hdlc frames with address fields that do not match any of the address combinations, are ignored by the escc8. in the case of a 1-byte address, ral1 and ral2 will be used as comparison registers. according to the x.25 lapb protocol, the value in ral1 will be interpreted as command and the value in ral2 as response. in version 2 and upwards the address bytes can be masked to allow selective broadcast frame recognition. for further information see chapter 2.3.4.10 .
sab 82538 saf 82538 semiconductor group 53 non-auto-mode (mode: mds1, mds0 = 01) characteristics: address recognition, arbitrary window size. all frames with valid addresses (address recognition identical to auto-mode) are forwarded directly via the rfifo to the system memory. the hdlc control field, data in the i-field and an additional status byte are temporarily stored in the rfifo. the hdlc control field and additional information can also be read from special registers (rhcr, rsta). in non-auto-mode, all frames with a valid address are treated similarly. in version 2 upward the address bytes can be masked to allow selective broadcast frame recognition. for further information see chapter 2.3.4.10 . transparent mode 1 (mode: mds1, mds0, adm = 101) characteristics: address recognition high byte only the high byte of a 2-byte address field will be compared.the address byte is compared with the fixed value feh or fch (group address) as well as with two individually programmable values in rah1 and rah2 registers. the whole frame excluding the first address byte will be stored in rfifo. ral1 contains the second and rhcr the third byte following the opening flag. in version 2 and upwards the address bytes can be masked to allow selective broadcast frame recognition. for further information see chapter 2.3.4.10 . transparent mode 0 (mode: mds1, mds0, adm = 100) characteristics: no address recognition no address recognition is performed and each frame will be stored in the rfifo. ral1 contains the first and rhcr the second byte following the opening flag. extended transparent modes 0, 1 (mode: mds1, mds0 = 11) characteristics: fully transparent in extended transparent modes, fully transparent data transmission/reception without hdlc framing is performed, i.e. without flag generation/recognition, crc generation/ check, or bit-stuffing. this allows user specific protocol variations. data transmission is always performed out of the xfifo. in extended transparent mode 0 (adm = 0), data reception is done via the ral1 register, which always contains the current data byte assembled at the r d pin. in extended transparent mode 1 (adm = 1), the receive data are additionally shifted into the rfifo.
sab 82538 saf 82538 semiconductor group 54 receive data flow (summary) the following figure gives an overview of the management of the received hdlc frames in the different operating modes. figure 19 receive data flow of escc8
sab 82538 saf 82538 semiconductor group 55 transmit data flow two different types of frames can be transmitted: C frames and C transparent frames as shown below. figure 20 transmit data flow of escc8 for i-frames (command xif via cmdr register), the address and control fields are generated autonomously by the escc8 and the data in the xfifo is entered into the information field of the frame. this is possible only if the escc8 is operated in the automode. for transparent frames (command xtf via cmdr register), the address and the control fields have to be entered in the xfifo as well. this is possible in all operating modes and used also in auto-mode for sending u-frames. version 2 upward: if ccr3.xcrc is set, the crc checksum will not be generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two or four bytes. the transmitted frame will be closed automatically only with a (closing) flag. note: the escc8 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not.
sab 82538 saf 82538 semiconductor group 56 2.3.2 procedural support (layer-2 functions) when operating in the auto mode, the escc8 offers a high degree of protocol support. in addition to address recognition, the escc8 autonomously processes all (numbered) s- and i-frames (prerequisite window size 1) with either normal or extended control field format (modulo 8 or modulo 128 sequence numbers - selectable via rah2 register). the following functions will be performed: l updating of transmit and receive counter l evaluation of transmit and receive counter l processing of s commands l flow control with rr/rnr l generation of responses l recognition of protocol errors l transmission of s commands, if acknowledgement is not received l continuous status query of remote station after rnr has been received l programmable timer/repeater functions. in addition, all unnumbered frames are forwarded directly to the processor. the logical link can be initialized by software at any time (reset hdlc receiver, rhr-command). additional logical connections can be operated in parallel by software. 2.3.2.1 full-duplex lapb/lapd operation initially (i.e. after reset), the lap controllers of the eight serial channels are configured to function as a combined (primary/secondary) station, where they autonomously perform a subset of the balanced x.25 lapb/isdn lapd protocol. reception of frames the logical processing of received s-frames is performed by the escc8 without interrupting the cpu. the cpu is merely informed by interrupt of status changes in the remote station (receive ready/not receive ready) and protocol errors (unacceptable n(r), or s-frame with i field). i-frames are also processed autonomously and checked for protocol errors. the i-frame will not be accepted in the case of sequence errors (no interrupt is forwarded to the cpu), but is immediately confirmed by an s response. if the cpu sets the escc8 into a receive not ready status, an i-frame will not be accepted (no interrupt) and an rnr response is transmitted. u frames are always stored in the rfifo and forwarded directly to the cpu. the logical sequence and the reception of a frame in auto mode is illustrated in figure 21. note: the state variables n(s), n(r) are evaluated within the window size 1, i.e. the escc8 checks only the least significant bit of the receive and transmit counter regardless of the selected modulo count.
sab 82538 saf 82538 semiconductor group 57 figure 21 processing of received frames in auto mode
sab 82538 saf 82538 semiconductor group 58 transmission of frames the escc8 autonomously transmits s commands and s responses in the auto mode. either transparent or i-frames can be transmitted by the user. the software timer has to be operated in the internal timer mode to transmit i-frames. after the frame has been transmitted, the timer is self-started, the xfifo is inhibited, and the escc8 waits for the arrival of a positive acknowledgement. this acknowledgement can be provided by means of an s- or i-frame. if no positive acknowledgment is received during time t 1, the escc8 transmits an s command ( p = 1), which must be answered by an s response ( f = 1). if the s response is not received, the process is performed n1 times (in hdlc known as n2, refer to register timr). upon the arrival of an acknowledgement or after the completion of this poll procedure the xfifo is enabled and an interrupt is generated. interrupts may be triggered by the following: l message has been positively acknowledged (alls interrupt) l message must be repeated (xmr interrupt) l response has not been received (tin interrupt) additionally, xpr interrupts are generated which indicate that new data can be written to the xfifo. using xpr enables high data rates, e.g. in conjunction with back-to-back frames or shared flags. in auto-mode, however, only when the alls interrupt has been issued may data of a new frame be written to the xfifo! upon arrival of an rnr frame, the software timer is started and the status of the remote station is polled periodically after expiration of t 1, until the status receive ready has been detected. the user is informed via the appropriate interrupt. if no response is received after n1 times, a tin interrupt, and t 1 clock periods thereafter an alls interrupt is generated and the process is terminated. note: the internal timer mode should only be used in the auto mode. transparent frames can be transmitted in all operating modes. after the transmission of a transparent frame the xfifo is immediately released, which is confirmed by interrupt (xpr). in this case, time monitoring can be performed with the timer in the external timer mode.
sab 82538 saf 82538 semiconductor group 59 figure 22 timer procedure / poll cycle
sab 82538 saf 82538 semiconductor group 60 examples the interaction between escc8 and the cpu during transmission and reception of i-frames is illustrated in figure 23 , the flow control with rr/rnr during reception of i-frames in figure 24 , and during transmission of i-frames in figure 25 . both the sequence of the poll cycle and protocol errors are shown in figure 26 . figure 23 transmission/reception i-frames figure 24 flow control/transmission
sab 82538 saf 82538 semiconductor group 61 figure 25 flow control/reception figure 26 s commands/protocol error
sab 82538 saf 82538 semiconductor group 62 2.3.2.2 half-duplex sdlc-nrm operation the lap controllers of the eight serial channels can be configured to function in a half- duplex normal response mode (nrm), where they operate as a slave (secondary) station, by setting the nrm bit in the xbch register of the corresponding channel. in contrast to the full-duplex lapb/lapd operation, where the combined (primary + secondary) station transmits both commands and responses and may transmit data at any time, the nrm mode allows only responses to be transmitted and the secondary station may transmit only when instructed to do so by the master (primary) station. the escc8 gets the permission to transmit from the primary station via an s-, or i-frame with the poll bit (p) set. the nrm mode can be profitably used in a point-to-multipoint configuration with a fixed master-slave relationship, which guarantees the absence of collisions on the common transmit line. it is the responsibility of the master station to poll the slaves periodically and to handle error situations. prerequisite for nrm operation is: l auto mode with 8-bit address field selected mode: mds1, mds0, adm = 000 l external timer mode mode: tmd = 0 l same transmit and receive addresses, since only responses can be transmitted, i.e. xad1 = xad2 = ral1 = ral2 (address of secondary) note: the broadcast address may be programmed in ral2 if broadcasting is required. in this case ral1 and ral2 are not equal. the primary station has to operate in transparent sdlc mode. reception of frames the reception of frames functions similarly to the lapb/lapd operation ( see 2.3.2.1 ). transmission of frames the escc8 does not transmit s-, or i-frames if not instructed to do so by the primary station via an s-, or i-frame with the poll bit set. the escc8 can be prepared to send an i-frame by the cpu by issuing an xif command (via cmdr) at any time. the transmission of the frame, however, will not be initiated by the escc8 until reception of either an l rr, or l i-frame with a poll bit set (p = 1).
sab 82538 saf 82538 semiconductor group 63 after the frame has been transmitted (with the final bit set), the xfifo is inhibited and the escc8 waits for the arrival of a positive acknowledgement. since the on-chip timer of the escc8 must be operated in the external mode (a secondary may not poll the primary for acknowledgements), timer supervision must be done by the primary station. upon the arrival of an acknowledgement the xfifo is enabled and an interrupt is forwarded to the cpu, either the C message has been positively acknowledged (alls interrupt), or the C message must be repeated (xmr interrupt). additionally, the timer can be used under cpu control to provide timer recovery of the secondary if no acknowledgements are received at all. note: the transmission of transparent frames is possible only if the permission to send is given by an s-frame ( p = 1) or i-frame. examples a few examples of escc8 / cpu interaction in the case of nrm mode are shown in figure 27 to 30 . figure 27 no data to send
sab 82538 saf 82538 semiconductor group 64 figure 28 data reception/transmission figure 29 data transmission (no error)
sab 82538 saf 82538 semiconductor group 65 figure 30 data transmission (error) 2.3.2.3 error handling depending on the error type, erroneous frames are handled according table 3 . table 3 error handling note: the station variables (v(s), v(r)) are not changed. frame type error type generated response generated interrupt record status i crc error aborted unexpected n(s) unexpected n(r) C C s-frame C rme rme C pce crc error abort C C s crc error aborted unexpected n(s) with i-field C C C C C C pce pce C C C C
sab 82538 saf 82538 semiconductor group 66 2.3.3 sdlc loop as a special variant of ibms sdlc protocol the sdlc loop is used to connect several secondary (= slave) stations to one primary (= master) station. different from standard hdlc, a reserved bit sequence is defined as end of poll sequence (eop = one 0 bit, followed by at least 7 1 bits). note that in standard hdlc this sequence is defined as abort sequence, therefore with sdlc loop frame abortion is not available. the escc8 facilitates entering and leaving the loop. in contrast to the protocol support described above, autonomous processing of s- and i-frames is not implemented by the circuit but is left to software. prerequisite for correct operation is l sdlc loop mode enabled (register ccr0) l normal response mode selected (xbch:nrm = 1) l non-auto-mode or transparent mode with 8-bit address field selected l external timer mode l nrz or nrzi data encoding enabled (register ccr0); no bus configuration l r clk = t clk l interframe timefill = flags figure 31 sdlc loop the loop is formed by connecting t d output of one station to the r d input of the next one ( refer to figure 31 ). this configuration is physically a loop, but logically a point-to- multipoint configuration. in every secondary station data flow from r d to t d is handled depending on secondarys current state as follows: l initially, rxd and txd are connected together with gate delay ( off loop state). data sent out from the primary is passed on by every secondary to the next one. thus, data is transparent to all secondaries.
sab 82538 saf 82538 semiconductor group 67 l after reception of an eop sequence a secondary can go to the on loop state. as opposed to the off loop state, all data is forwarded to the next station with one bit delay. l if a secondary is requested (polled) by the primary to transmit data or responses, it has to wait for reception of a further eop sequence. by flipping the seventh 1 of the eop sequence to 0 it generates a flag sequence and consequently all following secondary stations are inhibited from sending. simultaneously, rxd is disconnected from txd and transmission of a frame (or several frames) may start ( active on loop state). after terminating transmission the station reconnects rxd to txd. thus, an eop sequence is formed and another station may start data transmission. processing the eop sequences is handled automatically by the escc8: commands (glp, galp in register ccr1) and state indications (interrupts eop, olp, aolp in register isr1) are provided to control and monitor the state of the escc8 as secondary station. figure 32 shows the state diagram for the secondary. note that in order to be able to hold active on loop state flags has to be selected as interframe time fill, as opposed to idle. note: the primary station has to operate in standard sdlc mode. figure 32 state diagram of sdlc loop/secondary reception of frames sdlc loop as special variant of the sdlc protocol works in half-duplex normal response mode, that means that data transmission and data reception at the same time is not permitted. normally, data reception is only possible in the on loop state. the escc8, however, allows data reception in every state. activation/deactivation of the receiver is effected by the user by programming the rac bit in register mode.
sab 82538 saf 82538 semiconductor group 68 transmission of frames sending frames is only possible in the active on loop state. here, transmission can start with the xtf command. if necessary, flags as interframe timefill are inserted before the current frame begins (the modified eop and the first flag may share a 0). after finishing frame transmission, flags as interframe timefill are again sent until the go active on loop command (galp) is reset. by returning to on loop state an eop sequence is formed, the transmitter is disabled and r d is connected to t d again with one bit delay. note: xtf or xif may be issued before the active on loop state is reached. in this case, transmission starts immediately after entering the active on loop state. the opening flag of the first frame is sent out immediately following after the modified eop sequence (both may share a 0). 2.3.4 special functions 2.3.4.1 shared flags the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. the shared flag feature is enabled by setting bit sflg in control register ccr1. 2.3.4.2 preamble transmission if enabled via register ccr3, a programmable 8-bit pattern (register pre) is transmitted with a selectable number of repetitions after interframe timefill transmission is stopped and a new frame is ready to be sent out. note: zero bit insertion is disabled during preamble transmission. to guarantee correct function the programmed preamble value should be different from receive address byte values defined for any of the connected stations. 2.3.4.3 crc-32 in hdlc/sdlc mode, error protection is done by crc generation and checking. in standard applications, crc-ccitt algorithm is used. the frame check sequence at the end of each frame consists of two bytes of crc checksum. if required, the crc-ccitt algorithm can be replaced by the crc-32 algorithm, enabled via register ccr2. in this case the frame check sequence consists of four bytes.
sab 82538 saf 82538 semiconductor group 69 2.3.4.4 extended transparent transmission and reception when programmed in the extended transparent mode via the mode register (mds1, mds0 = 11), each channel of the escc8 performs fully transparent data transmission and reception without hdlc framing, i.e. without l flag insertion and deletion l crc generation and checking l bit-stuffing. in order to enable fully transparent data transfer, rac bit in mode has to be reset and ff h has to be written to xad1, xad2 and rah2. data transmission is always performed out of xfifo by directly shifting the contents of xfifo via the serial transmit data pin (t d). transmission is initiated by setting cmdr:xtf (08 h ); end of transmission is indicated by isr1:exe (10 h ). in receive direction, the character last assembled via receive data line (r d) is available in ral1 register. additionally, in extended transparent mode 1 (mode: mds1, mds0, adm = 111), received data is shifted into rfifo. this feature can be profitably used e.g. for: l user specific protocol variations l line state monitoring, or l test purposes, in particular for monitoring or intentionally generating hdlc protocol rule violations (e.g. wrong crc) character or octet boundary synchronization can be achieved by using clock mode 1 with an external receive strobe input to pin cd. 2.3.4.5 cyclic transmission (fully transparent) if the extended transparent mode is selected, the escc8 supports the continuous transmission of the contents of the transmit fifo. after having written 1 to 32 bytes to xfifo, the command xrep.xtf.xme via the cmdr register (bit 70 = 00101010 = 2a h ) forces the escc8 to repeatedly transmit the data stored in xfifo via t d pin. the cyclic transmission continues until a reset command (cmdr: xres) is issued, after which continuous 1-s are transmitted. note: in dma-mode the command xrep and xtf has to be written to cmdr.
sab 82538 saf 82538 semiconductor group 70 2.3.4.6 continuous transmission (dma mode only) if data transfer from system memory to the escc8 is done by dma (dma bit in xbch set), the number of bytes to be transmitted is usually defined via the transmit byte count registers (xbch, xbcl: bits xbc11xbc0). setting the transmit continuously (xc) bit in xbch, however, the byte count value is ignored and the dma interface of escc8 will continuously request for transmit data any time 32 new bytes can be entered in xfifo. this feature can be used e.g. to transmit frames of length higher than the byte count specified by xbch, xbcl (frames with more than 4096 bytes). note: if the xc bit is reset during continuous transmission, the transmit byte count becomes valid again, and the escc8 will request the amount of dma transfers programmed via xbc11..xbc0. otherwise, the continuous transmission and the generation of dma requests is stopped when a data underrun condition occurs in xfifo. instead of crc, continuous 1-s (idle) are transmitted thereafter. 2.3.4.7 receive length check feature the escc8 offers the possibility to supervise the maximum length of received frames and to terminate data reception in case this length is exceeded. this feature is controlled via the special receive length check register (rlcr). the function is enabled by setting the rc (receive check) bit in rlcr and programming the maximum frame length via bits rl6rl0. the maximum receive length can be determined as a multiple of 32-byte blocks as follows: max.length = (rl + 1) 32 where rl is the value written to rl6rl0. all frames exceeding this length are treated as if they had been aborted by the remote station, i.e. the cpu is informed via an l rme interrupt, and the l rab bit in rsta register is set. to distinguish this from the case where an abort sequence is indeed received (sent by the remote station), the receive byte count registers rbch, rbcl will contain a value exceeding the maximum receive length (via rl6...rl0) by one or two bytes.
sab 82538 saf 82538 semiconductor group 71 2.3.4.8 one bit insertion similar to the zero bit insertion (bit-stuffing) mechanism, as defined by the hdlc protocol, the escc8 offers a completely new feature of inserting/deleting a one after seven consecutive zeros in the transmit/receive data stream, if the serial channel is operating in a bus configuration. this method is useful if clock recovery is to be performed by dpll. since only nrz data encoding is supported in a bus configuration, there are possibly long sequences without edges in the receive data stream in case of successive 0-s received, and the dpll may lose synchronization. using the one bit insertion feature by setting the oin bit in the ccr1 register, however, it is guaranteed that at least after C 5 consecutive 1-s a 0 will appear (bit-stuffing), and after C 7 consecutive 0-s a 1 will appear (one insertion) and thus a correct function of the dpll is ensured. note: as with the bit-stuffing, the one insertion is fully transparent to the user, but it is not in accordance with the hdlc protocol, i.e. it can only be applied in proprietary systems using circuits that also implement this function, such as the sab 82532. 2.3.4.9 crc on/off feature (version 2 upward) as an option in non-auto mode or transparent mode 0, the internal handling of received and transmitted crc checksum can be influenced via control bits ccr3.rcrc and ccr3.xcrc. receive direction the received crc checksum is always assumed to be in the 2 (crc-ccitt) or 4 (crc-32) last bytes of a frame, immediately preceding a closing flag. in the version 1 of escc8 a check is performed on the crc but the received crc bytes are not transferred to the rfifo. in version 2 upwards, if ccr3.rcrc is set, the received crc checksum will be written to rfifo where it precedes the frame status byte (contents of register rsta). the received crc checksum is additionally checked for correctness. if non-auto mode is selected, the limits for valid frame check are modified (refer to description of bit rsta.vfr). transmit direction if ccr3.xcrc is set, the crc checksum is not generated internally. the checksum has to be provided via the transmit fifo (xfifo) as the last two or four bytes. the transmitted frame will only be closed automatically with a (closing) flag. note: the escc8 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not.
sab 82538 saf 82538 semiconductor group 72 2.3.4.10 receive address handling (version 2 upward) mask for address detection the receive address low/high byte (ral1/rah1) can be masked by setting the corresponding bits in the mask registers (aml/amh) to allow extended broadcast address recognition. this feature is applicable to all operating modes with address recognition (auto mode, non-auto mode and transparent mode 1). it is disabled if all bits of registers aml and amh are set to zero (reset value). the function of ral2/rah2 and detection of the fixed group address feh or fch if applicable to the selected operating mode remain unchanged. note: as a very useful option, the detected receive address can be pushed to rfifo (ccr3.radd). receive address pushed to rfifo as an option in the auto mode, non-auto mode and transparent mode 1, the address field of received frames can be pushed to rfifo (first one/two bytes of the frame). this function is especially useful in conjunction with the extended broadcast address recognition. it is enabled by setting control bit ccr3.radd. note: in this case the ratio of receive frequency (fr) to transmit frequency (fx) and to master clock frequency (fm) must fulfill: fr/fx < 1.5 (normal operation), fr/fm < 1.5 (master clock operation).
sab 82538 saf 82538 semiconductor group 73 2.4 asynchronous serial mode 2.4.1 character frame character framing is achieved by special start and stop bits. each data character is preceded by one start bit and terminated by one or two stop bits. the character length is selectable from 5 up to 8 bits. optionally, a parity bit can be added which complements the number of ones to an even or odd quantity (even/odd parity). the parity bit can also be programmed to have a fixed value (mark or space). figure 33 shows the asynchronous character format. figure 33 asynchronous character frame 2.4.2 data reception 2.4.2.1 operating modes the escc8 offers the flexibility to combine clock modes, data encoding and data sampling in many different ways. however, only definite combinations make sense and are recommended for correct operation: asynchronous mode prerequisites: l bit clock rate 16 selected (ccr1.bcr = 1) l clock mode 0, 1, 3b, 4, or 7b selected l nrz data encoding the receiver which operates with a clock rate equal to 16 times the nominal data bit rate, synchronizes itself to each character by detecting and verifying the start bit. since character length, parity and stop bit length is known, the ensuing valid bits are sampled.
sab 82538 saf 82538 semiconductor group 74 oversampling (3 samples) around the nominal bit center in conjunction with majority decision is provided for every received bit (including start bit). the synchronization lasts for one character, the next incoming character causes a new synchronization to be performed. as a result, the demand for high clock accuracy is reduced. two communication stations using the asynchronous procedure are clocked independently, their clocks need not be in phase or locked to exactly the same frequency but, in fact, may differ from one another within a certain range. isochronous mode prerequisites: l bit clock rate 1 selected (ccr1.bcr = 0) l clock mode 2, 3a, 6, or 7a (dpll mode) has to be used in conjunction with fm0, fm1 or manchester encoding. the isochronous mode uses the asynchronous character format. however, each data bit is only sampled once (no oversampling). in clock modes 0 and 1, the input clock has to be externally phase locked to the data stream. this mode allows much higher transfer rates. clock modes 3b, 4 and 7b are not recommended due to difficulties with bit synchronization when using the internal baud rate generator. in clock modes 2, 3a, 6, and 7a, clock recovery is provided by the internal dpll. correct synchronization of the dpll is achieved if there are enough edges within the data stream, which is generally ensured only if bi-phase encoding (fm0, fm1 or manchester) is used. 2.4.2.2 storage of data if the receiver is enabled, received data is stored in rfifo (the lsb is received first). moreover, the cd input may be used to control data reception. character length, the number of stop bits and the optional parity bit are checked. storage of parity bits can be disabled. errors are indicated via interrupts. additionally, the character error status (framing and parity) can optionally be stored in the rfifo ( refer to chapter 4.2.2 ). filling of the accessible part of rfifo is controlled by l a programmable threshold level l detection of the programmable termination character (optional). additionally, the time-out condition as optional status information indicates that a certain time (refer to register isr0) has elapsed since the reception of the last character.
sab 82538 saf 82538 semiconductor group 75 2.4.3 data transmission the selection of asynchronous or isochronous operation has no further influence on the transmitter. the bit clock rate is solely a dividing factor for the selected clock source. transmission of the contents of xfifo starts after the xf command is issued (the lsb is sent out first). further data is requested by interrupt (xpr) or dma. the character frame for each character, consisting of start bit, the character itself with defined character length, optionally generated parity bit and stop bit(s) is assembled. after finishing transmission (indicated by the all sent interrupt), idle (logical 1) is transmitted on t d. additionally, the cts signal may be used to control data transmission. 2.4.4 special features 2.4.4.1 break detection/generation break generation: on issuing the xbrk command (register dafo), the t d pin is immediately forced to physical 0 level with the first following clock edge, and released with the first clock edge after this command has been reset. break detection: the escc8 recognizes the break condition upon receiving consecutive (physical) 0s for the defined character length, the optional parity and the selected number of stop bits (zero character and framing error). the zero character is not pushed to rfifo. if enabled, the brk interrupt is generated. the break condition will be present until a 1 is received which is indicated by the break terminated interrupt (brkt). 2.4.4.2 flow control by xon/xoff (version 2 upward) programmable xon and xoff two eight-bit control registers (xon, xoff) contain the programmable values for xon and xoff characters. the number of significant bits in a register is determined by the programmed character length (right justified). two programmable eight-bit registers mxn and mxf serve as mask registers for the characters in xon and xoff, respectively: a 1 in a mask register has the effect that no comparison is performed between the corresponding bits in the received characters (dont cares) and the xon and the xoff register. at reset, the mask registers are zeroed, i.e. all bit positions are compared.
sab 82538 saf 82538 semiconductor group 76 a received character is considered to be recognized as a valid xon or xoff character C if it is correctly framed (correct length), C if its bits match the ones in the xon or xoff registers over the programmed character length, C if it has correct parity (if applicable). received xon and xoff characters are always stored in the receive fifo, as any other characters. in-band flow control of transmitted characters recognition of an xon or an xoff character causes always a corresponding maskable interrupt status to be generated (isr1.xon / imr1.xon; isr1.xoff / imr1.xoff). further action depends on the setting of a control bit mode.flon (flow control on): 0 no further action is automatically taken by the escc8. 1 the reception of an xoff character automatically turns off the transmitter after the currently transmitted character (if any) has been completely shifted out (xoff state). the reception of an xon character automatically makes the transmitter resume transmitting (xon state). after hardware reset, bit mode.flon is at 0. when bit mode.flon is made to go from 0 to 1, the transmitter is first in the xon state, until an xoff character is received. when bit mode.flon is made to go from 1 to 0, the transmitter always goes in the xon state, and transmission is only controlled by the user and by the cts input. the in-band flow control of the transmitter via received xon and xoff characters can be combined with control via cts pin, i.e. the effect of the cts pin is independent of whether in-band control is used or not. the transmitter is enabled only if cts is low and xon state has been reached. transmitter status bit the status bit flow control status (star.fcs) indicates the current state of the transmitter, as follows: 0 if the transmitter is in xon state 1 if the transmitter is in xoff state note: the transmitter cannot be turned off by software without disrupting data possibly remaining in the xfifo.
sab 82538 saf 82538 semiconductor group 77 flow control for received data after writing a character value to register tic (transmit immediate character) its contents are inserted in the outgoing character stream l immediately upon writing this register by the microprocessor if the transmitter is in idle state. if no further characters (xfifo contents) are to be transmitted, i.e. the transmitter returns to idle state after transmission of tic, an alls (all sent) interrupt will be generated. l after the end of a character currently being transmitted if the transmitter is not in idle state. this does not affect the contents of the xfifo. transmission of characters from xfifo is resumed after the contents of register tic are shifted out. transmission via this register is possible even when the transmitter is in xoff state (however, cts must be low). the tic register is an eight-bit register. the number of significant bits is determined by the programmed character length (right justified). parity value (if programmed) and selected number of stop bits are automatically appended, similar to the characters written in the xfifo. the usage of tic is independent of flow control, i.e. is not affected by bit mode.flon. to control access to register tic, an additional status bit star.tec (tic executing) is implemented which signals that transmission command of currently programmed tic is accepted but not completely executed. further access to register tic is only allowed if bit star.tec is 0. 2.4.4.3 continuous transmission (dma mode only) if data transfer from system memory to the escc8 is done by dma (dma bit in xbch set), the number of characters to be transmitted is usually defined via the transmit byte count registers (xbch, xbcl: bits xbc11xbc0). however, if the transmit continuously (xc) bit in xbch is set, the byte count value is ignored and the dma interface of escc8 will continuously request for transmit data any time 32 new characters can be stored in xfifo. note: if the xc bit is reset during continuous transmission, the transmit byte count becomes valid again, and the escc8 will request the amount of dma transfers programmed via xbc11xbc0. otherwise, the continuous transmission is stopped when a data underrun condition occurs in xfifo, i.e. the dma controller does not transfer further data to escc8. in this case continuous 1-s (idle) are transmitted.
sab 82538 saf 82538 semiconductor group 78 2.5 character oriented serial mode (monosync/bisync) 2.5.1 data frame character oriented protocols achieve synchronization between transmitting and receiving station by means of special syn characters. two examples are the monosync and ibms bisync procedures. bisync has two starting syn characters while monosync uses only one syn. figure 34 gives an example of the message format. figure 34 bisync message format the syn character, its length, the length of data characters and additional parity are programmable: l syn with 6 or 8 bit length (monosync), programmable via register synl. l 2 syn with 6 or 8 bit length each (bisync), programmable via registers synl and synh. l data character length may vary from 5 to 8 bits. l parity information (even/odd parity, mark, space) may be appended to the character.
sab 82538 saf 82538 semiconductor group 79 2.5.2 data reception the receiver is generally activated by setting the rac bit in the mode register. additionally, the cd signal may be used to control data reception. after issuing the hunt command, the receiver monitors the incoming data stream for the presence of specified syn character(s). however, data reception is still disabled. if synchronization is gained by detecting the syn character(s), scd interrupt is generated and all data is pushed to rfifo, i.e. control sequences, data characters and optional crc frame checking sequence (the lsb is received first). in normal operation, syn characters are excluded from storage to rfifo. syn character length can be specified independently of the selected data character length. if required, the character parity bit and/or parity status is fifoed together with each data byte. as an option, the loading of syn characters in rfifo may be enabled by setting the sload bit in register rfc. note that in this case syn characters are treated as data. consequently, for correct operation it must be guaranteed that syn character length equals the character length + optional parity bit. this is the users responsibility. filling of the accessible part of rfifo is controlled by a programmable threshold level. rfifo read is requested by interrupt (rpf) or dma. reception is stopped if 1. the receiver is deactivated by resetting the rac bit, or 2. the cd signal goes inactive (if carrier detect auto start is enabled), or 3. the hunt command is issued again, or 4. the receiver reset command (rres) is issued, or 5. a programmed termination character has been found (optional). on actions 1. and 2., reception remains disabled until the receiver is activated again. after this is done, and generally in cases 3. and 4., the receiver returns to the (non- synchronized) hunt state. in case 5. a hunt command has to be issued. reception of data is internally disabled until synchronization is regained. note: further checking of frame length, extraction of text or data information and verifying the frame checking sequence (e.g. crc) has to be done by the microprocessor.
sab 82538 saf 82538 semiconductor group 80 2.5.3 data transmission transmission of data written to xfifo is initiated after the transmit frame command (xf) is issued (the lsb is sent out first). additionally, the cts signal may be used to control data transmission. further data is requested by interrupt (xpr) or dma. the message frame is assembled by appending all data characters to the specified syn character(s) until transmit message end is detected (xme command in interrupt mode, or, in dma mode, when the number of characters specified in xbch, xbcl have been transferred). internally generated parity information may be added to each character (syn, crc and preamble characters are excluded). if enabled via crc append bit (capp), the internally calculated crc checksum (16 bit) is added to the message frame. selection between crc-16 and crc-ccitt algorithms is provided. for all characters which have to be included into crc calculation, the con flag has to be set to 1. this flag which controls the crc generator is fifoed together with each character. there is no need to modify con for every character loaded if continuous characters are to be either included into or excluded from crc calculation. note that C internally generated syn characters are always excluded from crc calculation, C crc checksum (2 bytes) is sent without parity. the internal crc generator is automatically initialized before transmission of a new frame starts. the initialization value is selectable. after finishing data transmission, interframe timefill (syn characters or idle) is automatically sent.
sab 82538 saf 82538 semiconductor group 81 2.5.4 special functions 2.5.4.1 preamble transmission if enabled via register ccr3, a programmable 8-bit pattern (register pre) is transmitted with a selectable number of repetitions after interframe timefill transmission is stopped and a new frame is ready to be sent out. note: if the preamble pattern equals the syn pattern, reception is triggered by the preamble. 2.5.4.2 continuous transmission (dma mode only) if data transfer from system memory to the escc8 is done by dma (dma bit in xbch set), the number of characters to be transmitted is usually defined via the transmit byte count registers (xbch, xbcl: bits xbc11xbc0). setting the transmit continuously (xc) bit in xbch, however, the byte count value is ignored and the dma interface of escc8 will continuously request for transmit data any time 32 new characters can be entered in xfifo. this feature can be used to transmit frames of length higher than the byte count specified by xbch, xbcl (frames with more than 4095 bytes). note: if the xc bit is reset during continuous transmission, the transmit byte count becomes valid again, and the escc8 will request the amount of dma transfers programmed via xbc11xbc0. otherwise, the continuous transmission and the generation of dma input requests is stopped when a data underrun condition occurs in xfifo. instead of crc, continuous 1-s (idle) are transmitted thereafter. 2.5.4.3 crc parity inhibit if the internal crc generator is not used for calculation of frame check sequence, an externally calculated checksum (16 bits) can be appended to the message frame without internally generated parity information, although parity is enabled for data characters. prerequisites are: l crc generator disabled (capp = 0), l con = 0 for all data characters which are to be included into parity generation (normal operation), l con = 1 for both bytes defining the crc checksum, l message end indication has to be issued after the checksum is written to xfifo. the programmed character length has no influence on this function.
sab 82538 saf 82538 semiconductor group 82 2.6 serial interface (layer-1 functions) the eight serial interfaces of the escc8 provide eight fully independent communication channels, supporting layer-1 functions to a high degree by various means of clock generation and clock recovery. note: since the eight serial channels are completely independent, the functions described in this document apply to all eight channels. for simplification purposes the indices 0 to 7 will usually be omitted from the signal names, and are implied. 2.6.1 clock modes the escc8 includes an internal oscillator (osc) as well as independent baud rate generator (brg) and digital phase locked loop (dpll) circuitry for each serial channel. the transmit and receive clock can be generated either C externally, and supplied via the r clk and/or t clk pins, or C internally, by means of the l osc and/or brg, and l dpll, recovering the receive (+ optionally transmit) clock from the received data stream. there are a total of 8 different clocking modes programmable via the ccr1 register, providing a wide variety of clock generation and clock pin functions, as shown in table 4. table 4 overview of clock modes clock type source generation mode receive clock rxclk pins dpll osc brg externally internally 0, 1, 5 2, 3a, 6, 7a 4 3b, 7b transmit clock txclk pins rxclk pins dpll brg ./. 16 osc brg externally internally 0a, 2a, 6a 1, 5 3a, 7a 2b, 6b 4 0b, 3b, 7b
sab 82538 saf 82538 semiconductor group 83 the transmit clock pins (txclk) may also output clock signals in certain clock modes if enabled via ccr2.toe. the clocking source for the dplls is always the internal brg; the scaling factor (divider) of the brg can be programmed through ccr2 and bgr registers between 1, 2, 4, 62048. the escc8s system clock is always derived from the transmit clock or from the master clock (if master clock mode is enabled). master clock capabilities a new clock source can be defined as master clock to allow full functionality of the microprocessor interface (access to all status and control registers and fifos, dma and interrupt support) independent from the receive and transmit clocks. this new function (enabled via bit ccr0.mce) is useful for modem applications where continuous generation of the receive and especially of the transmit clock cannot be guaranteed. the master clock has to be supplied via pin xtal1 (or a crystal connected to xtal1-2). depending on the version, the maximum clock rate is 10 mhz (sab 82538h-10) or 2 mhz (sab 82538h). notes: l the master clock is applicable to all clock modes except clock mode 5. for details refer to table 5 . l if bus configuration is selected in hdlc/sdlc mode (ccr0.sc2 .. 0), the one- insertion (ccr1.oin) cannot be used in conjunction with the master clock feature. l in sdlc loop mode the master clock option is not available. l the conditions for the ratio between transmit clock, master clock and receive clock frequencies must be fulfilled to guarantee correct function ( refer to the notes of table 5 ). l the internal timers run with the master clock. l the serial interface (transmitter and receiver) are not sequenced by the master clock however the fifos, dma-unit and timer are. clock mode 0 (external clocks) separate, externally generated receive and transmit clocks are supplied to the escc8 via their respective pins. the transmit clock can be directly supplied by pin txclk (mode 0a) or generated by the internal baud rate generator from the clock supplied by pin xtal1 (mode 0b). in the latter case, the transmit clock can be output via pin txclk.
sab 82538 saf 82538 semiconductor group 84 clock mode 1 (re./trm. strobes) externally generated, but identical receive and transmit clocks are supplied via rxclk. in addition, a receive strobe can be connected via cd and a transmit strobe via txclk. these strobe signals work on a per bit basis. the operating mode can be applied in time division multiplex applications or for adjusting disparate transmit and receive data rates. note: in extended transparent mode (hdlc/sdlc), the above mentioned strobe signals provide byte synchronization (byte alignment). clock mode 2 (rec. clock from dpll) the brg is driven by an external clock (r clk) and it delivers a reference clock of a frequency equal to 16 times the nominal bit rate for the dpll which in turn generates the receive clock. depending on the programming of the ccr2 register (bit ssel), the transmit clock will be either an external clock signal (t clk) or the clock delivered by the brg divided by 16. in the latter case, the transmit clock can be output via t clk. clock mode 3 (rec. and trm. clock from dpll) the brg is fed with an externally generated clock via r clk. depending on the value of bit ccr2.ssel the brg supplies either the reference clock of frequency equal to 16 times the nominal bit rate for the dpll, which generates both the receive and transmit clock, or, the receive and transmit clock directly. this clock can be output via t clk. clock mode 4 (osc-direct) the receive and transmit clocks are directly supplied by the osc. in addition, this clock can be output via t clk. clock mode 5 (time-slots) this operation mode has been designed for application in time-slot oriented pcm systems. note: clock mode 5 is only specified for version sab 82538h-10, but not for version sab 82538h. for correct operation only nrz coding should be used the receive and transmit clocks are common and must be supplied externally via rxclk pin. the escc8 receives and transmits only during certain time-slots C of programmable width (1256 bit, via rccr and xccr registers), and of programmable location with respect to a frame synchronization signal (via cd pin). one of up to 64 time-slots can be programmed independently for receive and transmit direction via tsar and tsax registers, and an additional clock shift of 07 bits via tsar, tsax and ccr2 register. together with bits xcs0 and rcs0 (lsb of clock shift), located in the ccr2 register, there are 9 bits to determine the location of a time- slot.
sab 82538 saf 82538 semiconductor group 85 depending to the value programmed via those bits, the receive/transmit window (time- slot) starts with a delay of 1 (minimum delay) up to 512 clock periods following the frame synchronization signal and is active for the number of clock periods programmed via rccr, xccr (number of bits to be received/transmitted within a time-slot) as shown in figure 35. if bit ccr2.toe is set, the transmit time-slot is indicated by a control signal via txclk, which is set to low during the transmit window. note: in hdlc/sdlc extended transparent modes above windows provide character synchronization (byte aligned). in extended transparent mode the width of the time-slots has to be nx8 bit. in all other modes they can be used to define windows down to a minimum length of one bit. figure 35 location of time-slots clock mode 6 (osc - rec. clock from dpll) this clock mode is identical to clock mode 2 except that the clock for the brg is delivered by the osc and must not be supplied externally. clock mode 7 (osc - rec. and trm. clock from dpll) similar to clock mode 3, but brg clock is provided by osc.
sab 82538 saf 82538 semiconductor group 86 summary the features of the different clock modes are summarized in table 5 . table 5 clock modes of escc8 notes: l if async mode is programmed, the baud rate depends on the bit clock rate (1 or 16) selected by bit ccr1.bcr: when bcr is set to 16, oversampling (3 samples) in conjunction with majority decision is performed. bcr has no effect when using clock mode 2, 3a, 6, or 7a. channel configur. clock sources control sources clock mode ccr1 cm2.cm1.cm0 ccr2, ssel master clock ccr0.mce=1 brg dpll rec trm cd r-strobe x-strobe frame-sync output via txclk (if ccr2.toe=1) 0a 0b 1 2a 2b 3a 3b 4 5 6a 6b 7a 7b 0 1 x 0 1 0 1 x x 0 1 0 1 osc osc osc osc osc osc osc osc C osc osc osc osc C osc C rxclk rxclk rxclk rxclk C C osc osc osc osc C C C brg brg brg C C C brg brg brg C rxclk rxclk rxclk dpll dpll dpll brg osc rxclk dpll dpll dpll brg txclk brg rxclk txclk brg/16 dpll brg osc rxclk txclk brg/16 dpll brg cd cd C cd cd cd cd cd C cd cd cd cd C C cd C C C C C (tsar) C C C C C C txclk C C C C C (tsax) C C C C C C C C C C C C cd C C C C C brg C C brg/16 dpll brg osc ts-control C brg/16 dpll brg clock mode receive transmit 0a 0b 1 3b, 7b 4 rxclk/bcr rxclk/bcr rxclk/bcr brg/bcr osc/bcr txclk brg rxclk/bcr brg/bcr osc/bcr
sab 82538 saf 82538 semiconductor group 87 l restrictions for frequency ratios between receive frequency (fr), transmit frequency (fx) and master clock frequency (fm): normal mode; clock mode 0, 2a, and 6a: fr/fx < 3 (*) master clock mode: fm/fx 3 2.5 for clocks (fm and fx) with about 50 % ( 5 %) duty cycle (*); fr/fm < 3 (**) (*) for unsymmetrical clocks higher ratios have to be provided, for example: (**) reduced to 1.5 if receive address is pushed to rfifo in hdlc/sdlc mode. there are no restrictions on the relative phases of the clocks. the conditions are valid independent of strobe signals or time-slot widths: i.e. in normal mode clock mode 1 always fulfils the condition, irrespective of how receive and transmit data are strobed. thus, by using strobes the above condition may always be fulfilled irrespective of the net data rates. l if one of the clock modes 0b, 4, 6 or 7 or the master clock is selected the internal oscillator (osc) is enabled which allows connection of an external crystal to pins xtal1-xtal2. the output signal of the osc can be used for one serial channel, or for all serial channels (independent baud rate generators and dplls). moreover, xtal1 alone can be used as input for an externally generated clock. 2.6.2 clock recovery (dpll) the escc8 offers the advantage of recovering the received clock from the received data by means of internal dpll circuitry, thus eliminating the need to transfer additional clock information via the serial link. for this purpose, the dpll is supplied with a reference clock from the brg which is 16 times the nominal data clock rate (clock mode 2, 3a, 6, 7a). the transmit clock may be obtained by dividing the output of the brg by a constant factor of 16 (clock mode 2b, 6b; bit ssel in ccr2 set) or also directly from the dpll (clock mode 3a, 7a). the main task of the dpll is to derive a receive clock and to adjust its phase to the incoming data stream in order to enable optimal bit sampling. the mechanism for clock recovery depends on the selected data encoding ( refer to chapter 2.6.4 ). fm (high time) fm (low time) fx (high time) fx (low time) ratio 50 % 50 % 70 % 30 % > 4 50 % 50 % 75 % 25 % > 5
sab 82538 saf 82538 semiconductor group 88 the following functions have been implemented to facilitate a fast and reliable synchronization: C interference rejection and spike filtering in the case where two or more edges appear in the data stream within a time period of 16 reference clocks, these are considered as interference and consequently no additional clock adjustment is performed. C phase adjustment in the case where an edge appears in the data stream within the pa fields of the time window, the phase will be adjusted by 1/16 of the data clock. C phase shift (nrz, nrzi only) in the case where an edge appears in the data stream within the ps fields of the time window, a second sampling of the bit is forced and the phase is shifted by 180 degrees. C edges in all other parts of the time window will be ignored. this operation facilitates a fast and reliable synchronization for most common applications. above all, it implies a very fast synchronization because of the phase shift feature: one edge on the received data stream is enough for the dpll to synchronize, thereby eliminating the need for synchronization patterns sometimes called preambles. however, in case of extremely high jitter of the incoming data stream the reliability of the clock recovery cannot be guaranteed. the version 2 of escc8 offers the option to disable the phase shift function for nrz and nrzi encodings by setting bit ccr3.psd. in this case, the pa fields are extended as shown in figure . now, the dpll is more insensitive to high jitter amplitudes but needs more time to reach the optimal sampling position. to ensure correct data sampling preambles should precede the data information. figures 36, and 38 explain the dpll algorithms used for the different data encodings.
sab 82538 saf 82538 semiconductor group 89 figure 36 dpll algorithm for nrz and nrzi coding with phase shift enabled (ccr3.psd = 0) figure 37 dpll algorithm for nrz and nrzi encoding with phase shift disabled (ccr3.psd = 1)
sab 82538 saf 82538 semiconductor group 90 figure 38 dpll algorithm for fm0, fm1 and manchester coding to supervise correct function when using bi-phase encoding, a status flag and a maskable interrupt inform about synchronous/asynchronous state of the dpll.
sab 82538 saf 82538 semiconductor group 91 2.6.3 bus configuration beside the point-to-point configuration, the escc8 effectively supports point-to- multipoint (pt-mpt or bus) configurations by means of internal idle and collision detection/ collision resolution methods. in a pt-mpt configuration, comprising a central station (master) and several peripheral stations (slaves), or in a multimaster configuration ( see figure 13 ), data transmission can be initiated by each station over a common transmit line (bus). in case more than one station attempt to transmit data simultaneously (collision), the bus has to be assigned to one station. C in hdlc/sdlc mode, a collision-resolution procedure is implemented by the escc8. bus assignment is based on a priority mechanism with rotating priorities. this allows each station a bus access within a predetermined maximum time delay (deterministic csma/cd), no matter how many transmitters are connected to the serial bus. C in bisync mode, the collision-resolution is implemented by the microprocessor. C in async mode, a bus configuration is not recommended. prerequisites for bus operation are: l nrz encoding l oring of data from every transmitter on the bus (this can be realized as a wired-or, using the txd open drain capability) l feedback of bus information (cxd input). the bus configuration is selected via the ccr0 register. note: central clock supply for each station is not necessary if both the receive and transmit clock is recovered by the dpll (clock modes 3a, 7a). this minimizes the phase shift between the individual transmit clocks. the bus mode can be operated independently of the clock mode, e.g. also during clock mode 1 (receive and transmit strobe). 2.6.3.1 bus access procedure the idle state of the bus is identified by eight or more consecutive 1s. when a device starts transmission of a frame, the bus is recognized to be busy by the other devices at the moment the first zero is transmitted (e.g. first zero of the opening flag in hdlc mode). after the frame has been transmitted, the bus becomes available again (idle). note: if the bus is occupied by other transmitters and/or there is no transmit request in the escc8, logical 1 will be continuously transmitted on t d.
sab 82538 saf 82538 semiconductor group 92 2.6.3.2 collisions during the transmission, the data transmitted on t d is compared with the data on c d. in case of a mismatch (1 sent and 0 detected, or vice versa) data transmission is immediately aborted, and idle (logical 1) is transmitted. hdlc/sdlc: transmission will be initiated again by the escc8 as soon as possible if the first part of the frame is still present in the xfifo. if not, an xmr interrupt is generated. since a zero (low) on the bus prevails over a 1 (high impedance) if a wired-or connection is implemented, and since the address fields of the hdlc frames sent by different stations normally differ from one another, the fact that a collision has occurred will be detected prior to or at the latest within the address field. the frame of the transmitter with the highest temporary priority (determined by the address field) is not affected and is transmitted successfully. all other stations cease transmission immediately and return to bus monitoring state. bisync: transmitter and xfifo are reset and pin t d goes to 1. the xmr interrupt is provided which requests the microprocessor to repeat the whole message or block of characters. async: bus configuration not recommended. note: if a wired or connection has been realized by an external pull-up resistor without decoupling, the data output (t d) can be used as an open drain output and connected directly to the c d input. for correct identification as to which frame is aborted and thus has to be repeated after an xmr interrupt has occurred, the contents of xfifo have to be unique, i.e. xfifo should not contain data of more than one frame as it could happen when servicing is done after an xpr interrupt. for this purpose the all sent interrupt (isr1.alls) instead of xpr has to be used to trigger the loading of data (for the next frame) into xfifo.
sab 82538 saf 82538 semiconductor group 93 2.6.3.3 priority (hdlc/sdlc mode only) to ensure that all competing stations are given a fair access to the transmission medium, once a station has successfully completed the transmission of a frame, it is given a lower level of priority. this priority mechanism is based on the requirement that a station may attempt transmitting only when a determined number of consecutive 1s are detected on the bus. normally, a transmission can start when eight consecutive 1s on the bus are detected (through pin c d). when an hdlc frame has been successfully transmitted, the internal priority class is decreased. thus, in order for the same station to be able to transmit another frame, ten consecutive 1s on the bus must be detected. this guarantees that the transmission requests of other stations are satisfied before a same station is allowed a second bus access. when ten consecutive 1s have been detected, transmission is allowed again and the priority class is increased (to eight 1s). inside a priority class, the order of transmission (individual priority) is based on the hdlc address, as explained in the preceding paragraph. thus, when a collision occurs, it is always the station transmitting the only zero (i.e. all other stations transmit a one) in a bit position of the address field that wins, all other stations cease transmission immediately. 2.6.3.4 timing modes if a bus configuration has been selected, the escc8 provides two timing modes, differing in the time interval between sending data and evaluation of the transmitted data for collision detection. l timing mode 1 (ccr0: sc1, sc0 = 01) data is output with the rising edge of the transmit clock via the txd pin, and evaluated 1/2 at the cxd pin clock period later with the falling clock edge. l timing mode 2 (ccr0: sc1, sc0 = 11) data is output with the falling clock edge and evaluated with the next falling clock edge. thus one complete clock period is available between the instant when data is output and collision detection.
sab 82538 saf 82538 semiconductor group 94 2.6.3.5 functions of rts output in clock modes 0, 1 and 4, the rts output can be programmed via ccr2 (soc bits) to be active when data (frame or character) is being transmitted. this signal is delayed by one clock period with respect to the data output t d, and marks all data bits that could be transmitted without collision. in this way a configuration may be implemented in which the bus access is resolved on a local basis (collision bus) and where the data are sent one clock period later on a separate transmission line. figure 39 request-to-send in bus operation note: for details on the functions of the rts pin refer to chapter 2.6.5 .
sab 82538 saf 82538 semiconductor group 95 2.6.4 data encoding the escc8 supports the following coding schemes for serial data: C non-return-to-zero (nrz) C non-return-to-zero-inverted (nrzi) C fm0 (also known as bi-phase space) C fm1 (also known as bi-phase mark) C manchester (also known as bi-phase) nrz: the signal level corresponds to the value of the data bit. by programming bit div (ccr2 register) the escc8 may made to transmit and receive data inverted. nrzi: a logical 0 is indicated by a transition and a logical 1 by no transition at the beginning of the bit cell. figure 40 nrz and nrzi data encoding fm0: an edge occurs at the beginning of every bit cell. a logical 0 has an additional edge in the center of the bit cell, a logical 1 has none. the transmit clock precedes the receive clock by 90?. fm1: an edge occurs at the beginning of every bit cell. a logical 1 has an additional edge in the center of the bit cell, a logical 0 has none. the transmit clock precedes the receive clock by 90?.
sab 82538 saf 82538 semiconductor group 96 figure 41 fm0 and fm1 data encoding manchester: in the first half of the bit cell the physical signal level corresponds to the logical value of the data bit. at the center of the bit cell this level is inverted. the transmit clock precedes the receive clock by 90?. the bit cell is shifted by 180? in comparison with fm coding. figure 42 manchester data encoding
sab 82538 saf 82538 semiconductor group 97 2.6.5 modem control functions ( rts/ cts, cd) 2.6.5.1 rts/ cts handshaking the escc8 provides two pins ( rts, cts) per serial channel supporting the standard rts-modem handshaking procedure for transmission control. a transmit request will be indicated by outputting logical 0 on the request-to-send output ( rts). it is also possible to control the rts output by software. after having received the permission to transmit ( cts) the escc8 starts data transmission. hdlc/sdlc and bisync: in the case where permission to transmit is withdrawn in the course of transmission, the frame is aborted and idle is sent. after transmission is enabled again by re-activation of cts, and if the beginning of the frame is still available in the escc8, the frame will be re-transmitted (self-recovery). however, if the permission to transmit is withdrawn after the data in the first xfifo pool has been completely transmitted and the pool is released, the transmitter and the xfifo are reset, the rts output is deactivated and an interrupt (xmr) is generated. note: for correct identification as to which frame is aborted and thus has to be repeated after an xmr interrupt has occurred, the contents of xfifo have to be unique, i.e. xfifo should not contain data of more than one frame, which could happen if transmission of a new frame is started by loading new data in xfifo and issuing a transmit command upon reception of xpr interrupt. for this purpose the all sent interrupt (isr1. alls) instead of xpr has to be used to trigger the loading of data (for the next frame) into xfifo. async: in the case where permission to transmit is withdrawn, transmission of the current character is completed. after that, idle is sent. after transmission is enabled again by re-activation of cts, the next available character is sent out. note: in the case where permission to transmit is not required, the cts input can be connected directly to v ss . additionally, any transition on the cts input pin will generate an interrupt indicated via the isr1 register, if this function is enabled by setting the csc bit in the imr1 register.
sab 82538 saf 82538 semiconductor group 98 figure 43 rts C cts handshaking beyond this standard rts function, signifying a transmission request of a frame (request to send), the rts output may be programmed for a special function via soc1, soc0 bits in the ccr2 register, provided the serial channel is operating in a bus configuration in clock mode 0 or 1. l if soc1, soc0 bits are set to 11, the rts output is active (= low) during the reception of a frame. l if soc1, soc0 bits are set to 10, the rts output function is disabled and the rts pin remains always high. 2.6.5.2 carrier detect (cd) receiver control similar to the rts/ cts control for the transmitter, the escc8 supports the carrier detect modem control function for the serial receivers, if the carrier detect auto start (cas) function is programmed by setting the cas bit in the xbch register. this function is always available in clock modes 0, 2, 3, 4, 6, 7 via the cd pin. in clock mode 1 the cd function is not supported. see table 5 for an overview. if the cas function is selected, the receiver is enabled and data reception is started when the cd input is detected to be high. if cd input is set to low, reception of the current character (byte) is still completed.
sab 82538 saf 82538 semiconductor group 99 2.6.6 test mode to provide for fast and efficient testing, the escc8 can be operated in a test mode by setting the tlp bit in the mode register. the on-chip serial input and output (t d-r d) are connected, generating a local loopback. as a result, the user can perform a self-test of the escc8. 2.7 universal port four general purpose bi-directional parallel ports are provided on pins pa0-7, pb0-7, pc0-7 and pd0-3. every pin is separately programmable via the port configuration register pcr to operate as an output or an input. if defined as output, the state of the pin is directly controlled via port value register pvr. a read-back is also provided. if defined as input, the state of the pin is monitored. the value is readable via pvr. all changes may be (if desired) indicated via interrupt. assigned registers: port interrupt status register (pis) and port interrupt mask register (pim).
sab 82538 saf 82538 semiconductor group 100 3 operational description 3.1 reset the escc8 is forced into the reset state if the res pin is set high for at least 5 microseconds. during reset, the escc8 is temporarily in the power-up mode, and a subset of the registers is initialized with defined values. during hardware reset C all uni-directional output stages are in high-impedance state. C all bi-directional output stages (data bus) are in high-impedance state if signals rd and inta are high, C output xtal2 is high-impedance if input xtal1 is high (the internal oscillator is disabled during reset). after reset, the escc8 is in power-down mode, and the following registers contain defined values: register reset value meaning ccr0 00 h C power down mode C hdlc/sdlc mode C nrz coding ccr1 00 h C no shared flags C no sdlc loop function C t d pins are open drain outputs C pt C pt with idle as interframe time fill C clock mode 0 ccr2 00 h C rts pin standard function C read/write exchange disabled C crc-32 disabled C no data inversion ccr3 00 h C no preambles C crc reset level is ffff h C no address to rfifo C no crc-bytes to rfifo C transmit crc off
sab 82538 saf 82538 semiconductor group 101 mode 00 h C auto/mode with 1 byte address field C external timer mode, timer resolution: k = 32768 C receiver active C rts output controlled by escc8 C no test loop imr0 imr1 pim ff h ff h ff h C all interrupts masked ipc 00 h C interrupt pin int is an open drain output C slave cascading mode is enabled C slave address is set to 00 h pcr ff h C all pins of the universal port are inputs iva 00 h C interrupt vector address is set to 00 h pre 00 h C preamble value is set to 00 h xbch 00 h C interrupt controlled data transfer (dma disabled) C full/duplex lapb/lapd operation of lap controller C carrier detect auto start of receiver disabled star 48 h C xfifo write enabled C receive line inactive C no commands executing aml/mxn amh/mxf 00 h 00 h C address mask disabled tsax tsar 00 h C time-slot number: 00 h C clock shift (together with ccr2 = 00 h ): 00 h xccr rccr 00 h C 1-bit time-slot register reset value meaning
sab 82538 saf 82538 semiconductor group 102 3.2 initialization after reset the cpu has to write a minimum set of registers and an optional set dependent on the required features and operating modes. first, the serial mode, the configuration of the serial port and the clock mode have to be defined via the ccr0 and ccr1 registers. the clock mode must be set before power- up (ccr1). the cpu may switch the escc8 between power-up and power-down mode. this has no influence upon the contents of the registers, i.e. the internal state remains stored. in power-down mode however, all internal clocks and the oscillator circuitry are disabled, no interrupts are forwarded to the cpu (interrupts of universal port excluded). this state can be used as a standby mode, when the escc8 is temporarily not used, thus substantially reducing power consumption. the escc8 should usually be initialized in power-down mode. the need for programming further registers depends on the selected features (serial mode, clock mode specific features, operating mode, address mode, user demands). table 6 gives an overview about initialization of the control registers. table 6 initialization of escc8 item registers comment clock mode clock mode specific features ccr0, ccr1 bgr, ccr2 tsar, tsax xccr, rccr for master clock mode for clock modes 2, 3, 4, 6, 7 for clock mode 5 serial mode ccr0 serial port configuration ccr0 ccr1 ccr2 encoding output driver select data inversion, rxd ? t d
sab 82538 saf 82538 semiconductor group 103 table 6 initialization of escc8 (contd) item registers comment serial mode specific features hdlc/sdlc async bisync mode, timr xad1, xad2 rah1, rah2 ral1, ral2 xbch ccr1 ccr2 ccr3 ccr4 pre rlcr ccr1 dafo rfc tcr mode synl, synh dafo rfc ccr3 pre tcr refer to table 7 nrm mode shared flags, itf / oin crc32 crc reset level, preamble crc/address-bytes to rfifo rfifo threshold preamble receive length check bit clock rate data format rfifo configuration termination character xon character xoff character bi-/mono-sync, slen syn character data format rfifo configuration crc, preamble preamble termination character user demands modem control lines parallel port interrupt features dma features timer (external mode) mode, ccr2 xbch pcr ipc iva imr0, imr1 pim xbch ccr2 mode, timr rts pins cd pins port configuration port configuration, slave addr. cascading mode interrupt vector address interrupt masks dma read/write exchange
sab 82538 saf 82538 semiconductor group 104 table 7 hdlc specific register setup operating mode address mode 2 byte address field (mode.adm = 1) 1 byte address field (mode.adm = 0) auto timr xad1 xad2 rah2 rah2 ral1 ral2 aml amh rah1 set to 00 h ral1 ral2 aml non auto rah2 rah2 ral1 ral2 aml amh rah1 set to 00 h ral1 ral2 aml transparent rah1 rah2 amh C C
sab 82538 saf 82538 semiconductor group 105 3.3 operational phase after having performed the initialization, the cpu switches each individual channel of the escc8 into operational phase by setting the pu bit in the ccr0 register. initially, the cpu should bring the transmitter and receiver into a defined state by issuing a transmitter reset command (cmdr.xres) and a receiver reset command (cmdr.rhr in hdlc/sdlc mode, cmdr.rres in async and bisync mode). if data reception should be performed, the receiver must be activated by setting the bit mode.rac. if no clear to send function is provided via a modem, the cts pin(s) of the escc8 must be connected directly to ground in order to enable data transmission. now the escc8 is ready to transmit and receive data. control of data transfer is mainly done by commands from cpu to escc8 via the cmdr register, and by interrupt indications from escc8 to cpu. additional status information, which does not trigger an interrupt, is available in the star register. 3.3.1 data transmission 3.3.1.1 interrupt mode in transmit direction 2 32 byte fifo buffers (transmit pools) are provided for each channel. after checking the xfifo status by polling the transmit fifo write enable bit (xfw in star register) or after a transmit pool ready (xpr) interrupt, up to 32 bytes may be entered by the cpu into the xfifo. hdlc/sdlc: the transmission of a frame can be started by issuing a xtf or xif command via the cmdr register. if enabled, a specified number of preambles (refer to registers ccr3 and pre) are sent out optionally before transmission of the current frame starts. if the transmit command does not include an end of message indication (cmdr: xme), the escc8 will repeatedly request for the next data block by means of a xpr interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. this process will be repeated until the cpu indicates the end of message per xme command, after which frame transmission is finished correctly by appending the crc and closing flag sequence. consecutive frames may share a flag (enabled via ccr1.sflg) or may be transmitted as back-to-back frames, if service of xfifo is quick enough. in case no more data is available in the xfifo prior to the arrival of xme, the transmission of the frame is terminated with an abort sequence and the cpu is notified per interrupt (isr1.xdu). the frame may also be aborted per software (cmdr: xres). the data transmission sequence, from the cpus point of view, is outlined in figure 44 .
sab 82538 saf 82538 semiconductor group 106 async: the transmission of character(s) can be started by issuing a xf command via the cmdr register. the escc8 will repeatedly request for the next data block by means of a xpr interrupt as soon as no more than 32 bytes are stored in the xfifo, i.e. a 32-byte pool is accessible to the cpu. transmission may be aborted per software (cmdr.xres). bisync: the transmission of a block can be started by issuing a xf command via the cmdr register. further handling of data transmission with respect to preamble transmission and command xme is similar to hdlc/sdlc mode. after xme command has been issued, the block is finished by appending the internally generated crc if enabled (refer to description of register ccr3). in case no more data is available in the xfifo prior to the arrival of xme, the transmission of the block is terminated with idle and the cpu is notified per interrupt (isr1.xdu). the block may also be aborted per software (cmdr.xres). the data transmission flow, from the cpus point of view, is outlined in figure 44. figure 44 interrupt driven data transmission (flow diagram)
sab 82538 saf 82538 semiconductor group 107 the activities at both serial and cpu interface during frame transmission (supposed frame length = 70 bytes) are shown in figure 45 . figure 45 interrupt driven transmission sequence example (hdlc) 3.3.1.2 dma mode prior to data transmission, the length of the next frame (or the next block of characters) to be transmitted must be programmed via the transmit byte count registers (xbch, xbcl). the resulting byte count equals the programmed value plus one byte, i.e. since 12 bits are provided via xbch, xbcl (xbc11xbc0) a frame length of 1 up to 4096 bytes (4 kbytes) can be selected. after this, data transmission can be initiated by command (xtf or xif in hdlc/sdlc mode, xf in async and bisync mode). the escc8 will then autonomously request the correct amount of write cycles by activating the drt line for as long as necessary, taking into account the selected data bus width (i.e. byte or word accesses). for a frame length of l = (n 32 + remainder) bytes (n = 0, 1,,128), block data transfers of 32 bytes/16 words or remainder ( ? 2) bytes (words) are requested whenever a 32-byte fifo half (transmit pool) is empty and accessible to the dma controller. the following figure gives an example of a dma driven transmission sequence with a supposed frame length of 70 bytes, i.e. programmed transmit byte count (xcnt) equal to 69 bytes.
sab 82538 saf 82538 semiconductor group 108 figure 46 dma driven transmission sequence example (hdlc) 3.3.2 data reception 3.3.2.1 interrupt mode also 2 32 byte fifo buffers (receive pools) are provided for each channel in receive direction. there are different interrupt indications concerned with the reception of data: hdlc/sdlc l rpf (receive pool full) interrupt, indicating that a 32-byte block of data can be read from rfifo and the received message is not yet complete. l rme (receive message end) interrupt, indicating that the reception of one message is completed, i.e. either * one message with less than 32 bytes, or the * last part of a message with more than 32 bytes is stored in the rfifo. in addition to the message end (rme) interrupt the following information about the received frame is stored by the escc8 in special registers and/or rfifo:
sab 82538 saf 82538 semiconductor group 109 table 8 status information after rme interrupt async, bisync l rpf (receive pool full) interrupt, indicating that a specified number of bytes (refer to register rfc) can be read from rfifo. l tcd (termination character detected) interrupt, indicating that reception has been terminated by reception of a specified character (refer to register tcr and bit rfc.tcde). additionally, the cpu can have access to contents of rfifo without having received an interrupt (and thereby causing tcd to occur) by issuing the rfifo read command (cmdr.rfrd). in addition to every received character the assigned status information parity bit (0/1), parity error (yes/no), framing error (yes/no, async only!) is optionally stored in rfifo. in addition to the end conditions (tcd interrupt or after rfrd command) the length of the last received data block is stored in register rbcl. note: for all serial modes! after the received data has been read from the rfifo, this must be explicitly acknowledged by the cpu issuing a rmc (receive message complete) command. the cpu has to handle the rpf interrupt before additional 32 bytes are received via the serial interface which would cause a receive data overflow condition. the following figure gives an example of an interrupt controlled reception sequence, assuming that a long frame (66 bytes) followed by two short frames (6 bytes each) is received. length of message (bytes) address combination and/or address field control field type of frame (command / response) crc result (good / bad) valid frame (yes / no) abort sequence recognized (yes / no) data overflow t rbch, rbcl t rsta t ral1 t rhcr t rsta t rsta t rsta t rsta t rsta register rfifo: last byte rfifo rfifo rfifo: last byte rfifo: last byte rfifo: last byte rfifo: last byte rfifo: last byte
sab 82538 saf 82538 semiconductor group 110 figure 47 interrupt driven reception sequence example (hdlc) 3.3.2.2 dma mode if the rfifo contains 32 bytes, the escc8 autonomously requests a block data transfer by dma by activating the drr line for as long as the start of the 32nd (byte access) or 16th (word access) read cycle. this forces the dma controller to continuously perform bus cycles till 32 bytes are transferred from the escc8 to the system memory. if the rfifo contains less than 32 bytes, the escc8 requests the correct amount of transfer cycles depending on the contents of the rfifo and taking into account the selected bus width. note: all available status information for each frame/data block after the end conditions (rme or tcd) and for each character is the same as described above. after the dma controller has been set up for the reception of the next frame, the cpu must issue a rmc command to acknowledge the completion of received data processing. the escc8 will not initiate further dma cycles by activating the drr line prior to the reception of rmc. in hdlc/sdlc mode the receive status register is automatically read from the rfifo with the last dma-read cycle of the received frame. the status information after a rme interrupt is the same as in the interrupt driven mode. the following figure gives an example of a dma controlled reception sequence, supposing that a long frame (66 bytes) followed by two short frames (6 bytes each) is received.
sab 82538 saf 82538 semiconductor group 111 figure 48 dma driven reception sequence example (hdlc)
sab 82538 saf 82538 hdlc mode semiconductor group 112 4 detailed register description in the register description the register addresses are specified by an offset relative to the base addresses, which are 000, 040, 080, 0c0, 100, 140, 180, 1c0 for the eight channels, respectively. 4.1 status/control registers in hdlc mode 4.1.1 register addresses table 9 register addresses in hdlc mode address (a8 a0) register channel 01234567 read write 000 01f 040 05f 080 9f 0c0 0df 100 11f 140 15f 180 19f 1c0 1df rfifo xfifo 020 060 0a0 0e0 120 160 1a0 1e0 star cmdr 021 061 0a1 0e1 121 161 1a1 1e1 rsta pre 022 062 0a2 0e2 122 162 1a2 1e2 mode 023 063 0a3 0e3 123 163 1a3 1e3 timr 024 064 0a4 0e4 124 164 1a4 1e4 xad1 025 065 0a5 0e5 125 165 1a5 1e5 xad2 026 066 0a6 0e6 126 166 1a6 1e6 rah1 027 067 0a7 0e7 127 167 1a7 1e7 rah2 028 068 0a8 0e8 128 168 1a8 1e8 ral1 029 069 0a9 0e9 129 169 1a9 1e9 rhcr ral2 02a 06a 0aa 0ea 12a 16a 1aa 1ea rbcl xbcl 02b 06b 0ab 0eb 12b 16b 1ab 1eb rbch xbch 02c 06c 0ac 0ec 12c 16c 1ac 1ec ccr0 02d 06d 0ad 0ed 12d 16d 1ad 1ed ccr1 02e 06e 0ae 0ee 12e 16e 1ae 1ee ccr2 02f 06f 0af 0ef 12f 16f 1af 1ef ccr3 030 070 0b0 0f0 130 170 1b0 1f0 tsax 031 071 0b1 0f1 131 171 1b1 1f1 tsar 032 072 0b2 0f2 132 172 1b2 1f2 xccr 033 073 0b3 0f3 133 173 1b3 1f3 rccr 034 074 0b4 0f4 134 174 1b4 1f4 vstr bgr 035 075 0b5 0f5 135 175 1b5 1f5 rlcr
sab 82538 saf 82538 hdlc mode semiconductor group 113 table 9 register addresses in hdlc mode (contd) *) all channel assigned addresses enable access to the same register(s) note: read access to unused register addresses: value should be ignored, write access to unused register addresses: should be avoided, or set to '00'hex. 4.1.2 register definitions receive fifo (read) rfifo (offset: 001f) reading data from the rfifo can be done in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. in versions 2 and upwards, the size of the accessible part of rfifo is determined by programming the bits ccr4.rft 1 0 (rfifo threshold level). it can be reduced from 32 bytes (reset value) down to 2 bytes (four values: 32, 16, 4, 2 bytes). l interrupt controlled data transfer (interrupt mode) selected if dma bit in xbch is reset. up to 32 bytes/16 words of received data can be read from the rfifo following an rpf or an rme interrupt. rpf interrupt: a fixed number of bytes/words to be read (version 1:32 bytes; version 2 upward: 32,16,4,2 bytes). the message is not yet complete. rme interrupt: the message is completely received. the number of valid bytes is determined by reading the rbcl, rbch registers. rfifo is released by issuing the receive message complete command (rmc). address (a8 a0) register channel 01234567 read write 036 076 0b6 0f6 136 176 1b6 1f6 aml 037 077 0b7 0f7 137 177 1b7 1f7 amh 038, 078, 0b8, 0f8, 138, 178, 1b8, 1f8 gis *) iva *) 039, 079, 0b9, 0f9, 139, 179, 1b9, 1f9 ipc *) 03a 07a 0ba 0fa 13a 17a 1ba 1fa isr0 imr0 03b 07b 0bb 0fb 13b 17b 1bb 1fb isr1 imr1 03c, 07c 0bc, 0fc 13c, 17c 1bc, 1fc pvrad 03d, 07d 0bd, 0fd 13d, 17d 1bd, 1fd pisa..d pima..d 03e, 07e 0be, 0fe 13e, 17e 1be, 1fe pcrad 03f 07f 0bf 0ff 13f 17f 1bf 1ff ccr4
sab 82538 saf 82538 hdlc mode semiconductor group 114 l dma controlled data transfer (dma mode) selected if dma bit in xbch is set. if the rfifo is filled up to its threshold level, the escc8 autonomously requests a block data transfer by dma by activating the drrn line until all read cycles are performed (the drrn line remains active up to the beginning of the last read cycle). this forces the dma controller to continuously perform bus cycles till all bytes/words are transferred from the escc8 to the system memory (level triggered transfer mode of dma controller). if the rfifo contains less bytes/words than defined via threshold level (one short frame or the last part of a long frame) the escc8 requests a block data transfer of size equal to the amount of data to be transferred. additionally, an rme interrupt is generated after the last byte has been transferred. further receiver dma requests are blocked until an rmc command is issued in response to rme. the valid byte count of the whole frame can be determined by reading the rbch, rbcl registers following the rme interrupt. note: addresses within the address space of the fifo point all to the current data word/ byte, i.e. the current data byte can be accessed with any address within the 32- byte range. transmit fifo (write) xfifo (offset: 00 1f) writing data to the xfifo can be done in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is transmitted first. l interrupt mode selected if dma bit in xbch is set to zero. up to 32 bytes/16 words of transmit data can be written to the xfifo following an xpr (or alls) interrupt. l dma mode selected if dma bit in xbch is set to one. prior to any data transfer, the actual byte count of the frame to be transmitted must be written to the xbch, xbcl registers by the user. if data transfer is then initiated via the cmdr register (command xtf or xif), the escc8 autonomously requests the correct amount of block data transfers (n*bw + remainder; bw = 32 or 16; n = 0, 1, ). note: addresses within the address space of the fifo's all point to the current data word/byte, i.e. the current data byte can be accessed with any address within the 32-byte range.
sab 82538 saf 82538 hdlc mode semiconductor group 115 status register (read) value after reset: 48 h xdov transmit data overflow more than 32 bytes have been written to the xfifo. this bit is reset by: C a transmitter reset command xres C or when all bytes in the accessible half of the xfifo have been moved into the inaccessible half. xfw transmit fifo write enable data can be written to the xfifo. xrnr transmit rnr (significant in auto-mode only!) indicates the status of the escc8. 0 receiver ready 1 receiver not ready rrnr received rnr (significant in auto-mode only!) indicates the status of the remote station. 0 receiver ready 1 receiver not ready rli receive line inactive neither flags as interframe time fill nor frames are received via the receive line. note: significant only in point-to-point configurations. cec command executing 0no command is currently being executed, the cmdr register can be written to. 1 a command (written previously to cmdr) is currently being executed, no further command can be temporarily written in cmdr register. note: cec will be active at most 2.5 transmit clock (or master clock) periods. if the escc8 is in power down mode cec will stay active. 70 star xdov xfw xrnr rrnr rli cec cts wfa (offset: 20)
sab 82538 saf 82538 hdlc mode semiconductor group 116 cts clear to send state this bit indicates the state of the cts pin. 0 cts is inactive (high) 1 cts is active (low) wfa wait for acknowledgment (significant in auto-mode only). indicates the wait for i frame acknowledgment status of escc8. command register (write) value after reset: 00 h note: the maximum time between writing to the cmdr register and the execution of the command is 2.5 clock cycles. therefore, if the cpu operates with a very high clock rate in comparison with the escc8's clock, it is recommended that the cec bit of the star register be checked before writing to the cmdr register to avoid any loss of commands. rmc receive message complete confirmation from cpu to escc8 that the current frame or data block has been fetched following an rpf or rme interrupt, thus the occupied space in the rfifo can be released. note: in dma mode, this command has to be issued after an rme interrupt, to enable the generation of further receiver dma requests. rhr reset hdlc receiver all data in the rfifo and the hdlc receiver is deleted. in auto-mode, additionally the transmit and receive sequence number counters are reset. rnr/xrep receiver not ready / transmission repeat the function of this command depends on the selected operation mode (mds1, mds0, adm bit in mode): auto mode: rnr determines the status of the escc8 receiver, i.e. whether a received frame is acknowledged via an rr or rnr supervisory frame in auto-mode. 0 receiver ready (rr) 1 receiver not ready (rnr) extended transparent mode 0, 1: xrep 70 cmdr rmc rhr rnr/ xrep sti xtf xif xme xres (offset: 20)
sab 82538 saf 82538 hdlc mode semiconductor group 117 if xrep is set to one together with xtf and xme (write 2a h to cmdr), the escc8 repeatedly transmits the contents of the xfifo (1 32 bytes) without hdlc framing fully transparently, i.e. without flag, crc or bit stuffing. the cyclic transmission is stopped with an xres command. sti start timer the internal timer is started. note: the timer is stopped by rewriting the timr register after start. xtf transmit transparent frame interrupt mode after having written up to 32 bytes to the xfifo, this command initiates the transmission of a transparent frame. an opening flag sequence is automatically added to the data by the escc8. dma mode after having written the length of the frame to be transmitted to the xbch, xbcl registers, this command initiates the data transfer from system memory to escc8 by dma. serial data transmission starts as soon as 32 bytes are stored in the xfifo or the transmit byte counter value is reached. xif transmit i-frame (used in auto-mode only!) initiates the transmission of an i-frame in auto-mode. additionally to the opening flag sequence, the address and control field of the frame is automatically added by escc8. xme transmit message end (used in interrupt mode only!) indicates that the data block written last to the transmit fifo completes the current frame. the escc8 can terminate the transmission operation properly by appending the crc and the closing flag sequence to the data. in dma mode, the end of the frame is determined by the transmit byte count in xbch, xbcl, thus, xme is not used in this case. xres transmitter reset xfifo is cleared of any data and an abort sequence (seven 1's) followed by interframe time fill is transmitted. in response to xres an xpr interrupt is generated. this command can be used by the cpu to abort a frame currently in transmission.
sab 82538 saf 82538 hdlc mode semiconductor group 118 preamble register (write) value after reset: 00 h this register defines the pattern which is sent out during preamble transmission (refer to register ccr3). note: it should be taken into consideration that zero bit insertion is disabled during preamble transmission. receive status register (read) note: rsta relates to the last received hdlc frame; it is copied into rfifo when end- of-frame is recognized (last byte of each stored frame). vfr valid frame determines whether a valid frame has been received. 1 valid 0 invalid an invalid frame is either C a frame which is not an integer number of 8 bits (n 8 bits) in length (e.g. 25 bits), or C a frame which is too short taking into account the operation mode selected via mode (mds1, mds0, adm) and the selected crc algorithm (ccr2.c32) and the selection of receive crc on/off (ccr3.rcrc) as follows: auto-/non-auto-mode (16 bit address), rcrc = 0 : 4 bytes (crc-ccitt) or 6 (crc-32) auto-/non-auto-mode (16 bit address), rcrc = 1 : 3-4 bytes (crc-ccitt) or 3-6 (crc-32) auto-/non-auto-mode (8 bit address), rcrc = 0 : 3 bytes (crc-ccitt) or 5 (crc-32) auto-/non-auto-mode (8 bit address), rcrc = 1 : 2-3 bytes (crc-ccitt) or 2-5 (crc-32) transparent mode 1: 3 bytes (crc-ccitt) or 5 (crc-32) transparent mode 0: 2 bytes (crc-ccitt) or 4 (crc-32) note: shorter frames are not reported. 70 pre pr7 pr0 (offset: 21) 70 rsta vfr rdo crc rab ha1 ha0 c/r la (offset: 21)
sab 82538 saf 82538 hdlc mode semiconductor group 119 rdo receive data overflow a data overflow has occurred during reception of the frame. additionally, an interrupt can be generated (refer to isr1.rdo/ imr1.rdo). crc crc compare/check 0 crc check failed; received frame contains errors. 1 crc check o.k.; received frame is error-free. rab receive message aborted the received frame was aborted from the transmitting station. according to the hdlc protocol, this frame must be discarded by the receiver station. ha1, ha0 high byte address compare significant only if 2-byte address mode has been selected. in operating modes which provide high byte address recognition, the escc8 compares the high byte of a 2-byte address with the contents of two individually programmable registers (rah1, rah2) and the fixed values fe h and fc h (broadcast address). dependent on the result of this comparison, the following bit combinations are possible: 10 rah1 has been recognized 00 rah2 has been recognized 01 broadcast address has been recognized note: if rah1, rah2 contain identical values, a match is indicated by '10'. c/r command/response significant only if 2-byte address mode has been selected. value of the c/r bit (bit in high address byte) in the received frame. the interpretation depends on the setting of the cri bit in the rah1 register. refer also to the description of rah1 register. la low byte address compare not significant in transparent and extended transparent operating modes. the low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two registers. (ral1, ral2). 0 ral2 has been recognized 1 ral1 has been recognized according to the x.25 lapb protocol, ral1 is interpreted as the address of a command frame and ral2 is interpreted as the address of a response frame.
sab 82538 saf 82538 hdlc mode semiconductor group 120 mode register (read/write) value after reset: 00 h mds1 mds0 mode select the operating mode of the hdlc controller is selected. 00 auto-mode 01 non auto-mode 10 transparent mode 11extended transparent mode adm address mode the meaning of this bit varies depending on the selected operating mode: auto-mode, non auto-mode defines the length of the hdlc address field. 0 8-bit address field 1 16-bit address field in transparent modes, this bit differentiates between two sub-modes: transparent mode 0 transparent mode 0; no address recognition. 1 transparent mode 1; high byte address recognition. extended transparent mode; without hdlc framing. 0 extended transparent mode 0 1 extended transparent mode 1 note: in extended transparent modes, the rac bit must be reset to enable fully transparent reception. 70 mode mds1 mds0 adm tmd rac rts trs tlp (offset: 22)
sab 82538 saf 82538 hdlc mode semiconductor group 121 tmd timer mode determines the operating mode of the timer. 0 external mode the timer is controlled by the cpu and can be started at any time by setting the sti bit in cmdr. 1 internal mode the timer is used internally by the escc8 for time-out and retry conditions in auto-mode (refer to the description of the timr register). rac receiver active switches the receiver to operational or inoperational state. 0 receiver inactive 1 receiver active in extended transparent modes this bit must be reset to enable fully transparent reception. rts request to send defines the state and control of rts pin. 0 the rts pin is controlled by the escc8 autonomously. rts is activated when a frame transmission starts and deactivated when transmission is completed. 1 the rts pin is controlled by the cpu. if this bit is set, the rts pin is activated immediately and remains active till this bit is reset. trs timer resolution selects the resolution of the internal timer (factor k , see description of timr register): 0 k = 32 768 1 k = 512 tlp test loop input and output of the hdlc channel are internally connected. (e.g. transmitter channel 0 - receiver channel 0)
sab 82538 saf 82538 hdlc mode semiconductor group 122 timer register (read/write) value (5 bits) sets the time period t 1 as follows: t 1 = k (value + 1) tcp where C k is the timer resolution factor which is either 32 768 or 512 clock cycles dependent on the programming of trs bit in mode. C tcp is the clock period of transmit data. cnt (3 bits) interpreted differently depending on the selected timer mode (bit tmd in mode). internal timer mode (mode.tmd = 1) C retry counter (in hdlc known as n2) cnt indicates the number of s-commands (max. 6) which are transmitted autonomously by the escc8 after expiration of time period t 1 , in case an i-frame is not acknowledged by the opposite station. if cnt is set to 7, the number of s-commands is unlimited. external timer mode (mode.tmd = 0) cnt plus value determine the time period t 2 after which a timer interrupt will be generated. the time period t 2 is t 2 = 32 k cnt tcp + t 1 . if cnt is set to 7, a timer interrupt is periodically generated after the expiration of t 1 . transmit address byte 1 (read/write) xad1 (and xad2) can be programmed with one individual address byte which is appended automatically to the frame by escc8 in auto-mode. the function depends on the selected address mode (bit adm in mode). 70 timr cnt value (offset: 23) 70 2-byte address xad1 xad1 (high byte) 0 (0) (offset: 24) 1-byte address xad1 xad1 (command)
sab 82538 saf 82538 hdlc mode semiconductor group 123 C 2-byte address field (mode.adm = 1) xad1 constitutes the high byte of the 2-byte address field. bit 1 must be set to 0. according to the isdn lapd protocol, bit 1 is interpreted as the c/r (command/ response) bit. this bit is manipulated automatically by the escc8 according to the setting of the cri bit in rah1: (in isdn lap-d, the high address byte is known as sapi). in accordance with the hdlc protocol, bit 0 should be set to 0, to indicate that the address field contains (at least) one more byte. C 1-byte address field (mode.adm = 0) according to the x.25 lapb protocol, xad1 is the address of a command frame. transmit address byte 2 (read/write) second individually programmable address byte. C 2-byte address (mode.adm = 1) xad2 constitutes the low byte of the 2 byte address field (in isdn lap-d, the low address byte is known as tei). C 1-byte address (mode.adm = 0) according to the x.25 lapb protocol, xad2 is the address of a response frame. note: xad1, xad2 registers are used only if the escc8 is operated in auto-mode. bit 1 (c/r) commands transmit 1 0 response transmit 0 1 cri = 1 cri = 0 70 2-byte address xad2 xad2 (low byte) (offset: 25) 1-byte address xad2 xad2 (response)
sab 82538 saf 82538 hdlc mode semiconductor group 124 receive address byte high register 1 (write) in operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in rah1 and rah2. in versions 2 and upwards, this register can be masked by setting the corresponding bits in the mask register amh to allow extended broadcast address recognition. this feature is applicable to all operating modes with address recognition. rah1 value of the first individual high address byte cri command/response interpretation the setting of the cri bit affects the meaning of the c/r bit in rsta as follows: important note: if 1-byte address field is selected in auto-mode, rah1 must be set to 00 h . 70 rah1 rah1 cri 0 (offset: 26) c/r meaning c/r value commands received 0 1 responses received 1 0 cri = 1 cri = 0
sab 82538 saf 82538 hdlc mode semiconductor group 125 receive address byte high register 2 (write) rah2 value of second individual high address byte. mcs modulo count select (valid in auto-mode only!) the mcs bit determines the hdlc control field format. 0 basic operation, one-byte control field (modulo 8) 1 extended operation, two-byte control field (modulo 128) note: when modulo 128 is selected, in auto mode the rhcr' register contains compressed information of the extended control field (see rhcr register description). rah1, rah2 registers are used in auto- and non-auto operating modes when a 2-byte address field has been selected (mode.adm = 1) and in transparent mode 0. receive address byte low register 1 (write or read) the general function (write or read) and the meaning or contents of this register depend on the selected operating mode: l auto-/non-auto-mode (16-bit address) - write access only: (read access not specified) ral1 can be programmed with the value of the first individual low address byte. l auto-/non-auto-mode (8-bit address) - write access only: (read access not specified) according to x.25 lapb protocol, the address in ral1 is considered as the address of a command frame. l transparent mode 1 (high byte address recognition) - read access only: (write access has no influence) ral1 contains the byte following the high byte of the address in the receive frame (i.e. the second byte after the opening flag). l transparent mode 0 (no address recognition) - read access only: (write access has no influence) ral1 contains the first byte after the opening flag (first byte of received frame). 70 rah2 rah2 mcs 0 (offset: 27) 70 ral1 ral1 (offset: 28)
sab 82538 saf 82538 hdlc mode semiconductor group 126 l extended transparent modes 0, 1 - read access only: (write access has no influence) ral1 contains the current data byte assembled from the r d pin, the hdlc receiver is by-passed (fully transparent reception without hdlc framing). in versions 2 upward, this register can be masked by setting the corresponding bits in the mask register aml to allow extended broadcast address recognition. this feature is applicable to all operating modes with address recognition. receive hdlc control register (read) value of the hdlc control field of the last received frame. note: rhcr is copied into rfifo for every frame. 70 rhcr rhcr (offset: 29) contents of rhcr mode modulo 8 (mcs = 0) modulo 128 (mcs = 1) auto mode, 1-byte address (u-frames) (note 1) control field control field in (note 2) auto mode, 2-byte address (u-frames) (note 1) control field control field in (note 2) auto mode, 1-byte address (i-frames) (note 1) control field control field in compressed form (note 3) auto mode, 2-byte address (i-frames) (note 1) control field control field in compressed form (note 3) non-auto mode, 1-byte address 2 nd byte after flag non-auto mode, 2-byte address 3 rd byte after flag transparent mode 1 3 rd byte after flag transparent mode 2 2 nd byte after flag
sab 82538 saf 82538 hdlc mode semiconductor group 127 note 1: s-frames are handled automatically and are not transferred to the microprocessor. note 2: for u-frames (bit 0 of rhcr = 1) the control field is as in the modulo 8 case. note 3: for i-frames (bit 0 of rhcr = 0) the compressed control field has the same format as in the modulo 8 case, but only the three lbss of the receive and transmit counters are visible: receive address byte low register 2 (write) value of the second individually programmable low address byte. if a one byte address field is selected, ral2 is considered as the address of a response frame according to x.25 lapb protocol. receive byte count low (read) together with rbch (bits rbc11 - rbc8), indicates the length of a received frame (14096 bytes). bits rbc4-0 indicate the number of valid bytes currently in rfifo. these registers must be read by the cpu following a rme interrupt. bit 7 6543210 n(r) p n(s) 0 70 ral2 ral2 (offset: 29) 70 rbcl rbc7 rbc0 (offset: 2a)
sab 82538 saf 82538 hdlc mode semiconductor group 128 transmit byte count low (write) together with xbch (bits xbc11xbc8) this register is used in dma mode only, to program the length (14096 bytes) of the next frame to be transmitted. in terms of the value xbc, programmed in xbc11xbc0 (xbc = 04095), the length of the block in number of bytes is: length = xbc + 1. this allows the escc8 to request the correct amount of dma cycles after an xtf or xif command in cmdr. received byte count high (read) value after reset: 000 xxxxx dma, nrm, cas these bits represent the read-back value programmed in xbch ov counter overflow more than 4095 bytes received. rbc11 C rbc8 receive byte count (most significant bits) together with rbcl (bits rbc7 rbc0) indicate the length of the received frame. 70 xbcl xbc7 xbc0 (offset: 2a) 70 rbch dma nrm cas ov rbc11 rbc8 (offset: 2b) see xbch
sab 82538 saf 82538 hdlc mode semiconductor group 129 transmit byte count high (write) value after reset: 000 xxxxx dma dma mode selects the data transfer mode of escc8 to/from system memory. 0 interrupt controlled data transfer (interrupt mode). 1 dma controlled data transfer (dma mode). nrm normal response mode valid in auto-mode only. determines the function of the lap controller: 0 full-duplex lapb/lapd operation 1 half-duplex nrm operation cas carrier detect auto start when set, a high on the cd pin enables the corresponding receiver and data reception is started. when not set, if not in clock mode 1 or 5, the cd pin can be used as a general input. xc transmit continuously only valid if dma mode is selected. if the xc bit is set, the escc8 continuously requests for transmit data ignoring the transmit byte count programmed via xbch, xbcl. xbc11 C xbc8 transmit byte count (most significant bits) valid only if dma mode is selected. together with xbcl (bits xbc7 xbc0), determine the length of the frame to be transmitted. 70 xbch dma nrm cas xc xbc11 xbc8 (offset: 2b)
sab 82538 saf 82538 hdlc mode semiconductor group 130 channel configuration register 0 (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. pu switches between power up and power down mode 0 power down (standby) 1 power up (active) mce master clock enable if this bit is set to 1, the clock provided via pin xtal1 works as master clock to allow full functionality of the microprocessor interface (access to all status and control registers and fifos, dma and interrupt support) independent of the receive and the transmit clocks. the internal oscillator in conjunction with a crystal on xtal1-2 can be used, too. the master clock option is not applicable in clock mode 5 or in sdlc loop mode. refer to table 5 for more details. note: the internal timers run with the master clock. sc2 C sc0 serial port configuration 000 nrz data encoding 001 bus configuration, timing mode 1 010 nrzi data encoding 011 bus configuration, timing mode 2 100 fm0 data encoding 101 fm1 data encoding 110 manchester data encoding 111 (not used) note: if bus configuration is selected, only nrz coding is supported. sm1 C sm0 serial mode 00 hdlc/sdlc mode 01 sdlc loop mode 10 bisync mode 11 async mode 70 ccr0 pu mce 0 sc2 sc1 sc0 sm1 sm0 (offset: 2c)
sab 82538 saf 82538 hdlc mode semiconductor group 131 channel configuration register 1 (read/write) value after reset: 00 h sflg enable shared flags if this bit is set, the closing flag of a preceding frame simultaneously becomes the opening flag of the following frame. galp go active on loop only used if sdlc loop is enabled. this bit enables transmission on an sdlc loop. 1 after detection of the next eop sequence, the escc8 goes to the sending on loop state by changing the seventh 1-bit of the eop sequence into a 0, thus creating a start flag, and by disconnecting the t d pin from the r d pin. the escc8 is now active on loop and can transmit frames as soon as data is available in the xfifo. the time between frames is always filled by sending continuous flags (independent from the value of bit ccr1.itf), thus occupying the loop. 0 the escc8 leaves the sending on loop state when the xfifo is empty by retransmitting data received on r d to t d (with one bit delay) after the closing flag has been transmitted (thus creating an eop sequence). glp go on loop only used if sdlc loop is enabled. this command controls entering and leaving the sdlc loop. 1 the escc8 enters the on loop state after detection of the next eop sequence by adding a 1-bit delay between receive and transmit path. the on loop state is prerequisite for sending frames on loop. 0 the escc8 leaves the on loop state by suppressing the 1-bit delay after detection of the next eop sequence. 70 ccr1 sflg galp glp ods itf/ oin cm2 cm0 (offset: 2d)
sab 82538 saf 82538 hdlc mode semiconductor group 132 ods output driver select defines the function of the transmit data pin (t d) 0 t d pin is an open drain output. 1 t d pin is a push-pull output. note: this feature is also valid for pin r d if it is switched to t d function via bit ccr2.soc1. itf/oin interframe time fill / one insertion the function of this bit depends on the selected serial port configuration (bit sc1): point-to-point configurations: itf determines the idle (= no data to send) state of the transmit data pin t d 0 continuous logical 1 is output 1 continuous flag sequences are output (01111110 bit patterns) bus configurations: oin when this bit is set, a one insertion (deletion) mechanism is activated: a 1 is inserted after seven consecutive 0s in the transmit data stream and a 1 is deleted after seven consecutive 0 in the receive data stream. similar to the hdlc bit-stuffing mechanism (inserting a 0 after five consecutive 1s), this enables clock information to be recovered from the receive data stream by means of a dpll even in the case of nrz encoding, because a transition at bit cell boundary occurs at least every 7 bits. the one insertion cannot be used in conjunction with the master clock option. note: in bus configurations, the itf is implicitly set to 0, i.e. continuous 1s are transmitted, and data encoding is nrz. cm2 C cmo clock mode selects one of 8 different clock modes: 000 clock mode 0 111 clock mode 7
sab 82538 saf 82538 hdlc mode semiconductor group 133 channel configuration register 2 (read/write) value after reset: 00 h the meaning of the individual bits in ccr2 depends on the clock mode selected via ccr1 as follows: note: unused bits have to be set to logical 0. soc1, soc0 special output control in a bus configuration (selected via ccr0), defines the function of pin rts as follows: 0x rts output is activated during transmission of a frame. 10 rts output is always high ( rts disabled). 11 rts indicates the reception of a data frame (active low). in a point-to-point configuration (selected via ccr0) the t d and r d pins may be flipped 0x data is transmitted on t d, received on r d (normal case). 1x data is transmitted on r d, received on t d. br9, br8 baud rate, bit 9-8 high order bits, see description of bgr register. xcs0, rcs0 transmit/receive clock shift, bit 0 together with bits xcs2, xcs1 (rcs2, rcs1) in tsax (tsar) the clock shift relative to the frame synchronization signal of the transmit (receive) time-slot can be adjusted. a clock shift of 0 7 bits is programmable. bdf baud rate division factor 0 the division factor of the baud rate generator is set to 1 (constant). 1 the division factor is determined by br9 - br0 bits in ccr2 and brg registers. ccr2 70 clock mode 0a, 1 soc1 soc0 0 ssel 0 rwx c32 div (offset: 2e) clock mode 0b,2,3,6,7 br9 br8 bdf ssel toe rwx c32 div clock mode 4 soc1 soc0 0 0 toe rwx c32 div clock mode 5 soc1 soc0 xcs0 rcs0 toe rwx c32 div
sab 82538 saf 82538 hdlc mode semiconductor group 134 ssel clock source select selects the clock source in clock modes 0, 2, 3, 6 and 7 ( refer to table 5 ). toe txclk output enable 0 t clk pin is input. 1 t clk pin is switched to output function if applicable to the selected clock mode ( refer to table 5 ). rwx read/write exchange valid only in dma mode. if this bit is set, the C rd and wr pins are internally exchanged (siemens/intel bus interface) C r/ w pin is inverted in polarity (motorola bus interface) while any dack input is active. this feature allows a simple interfacing to the dma controller. note: the rwx bit of all eight channels is ored. c32 enable crc-32 0 crc-ccitt is selected. 1 crc-32 is selected. div data inversion only valid if nrz data encoding is selected. data is transmitted and received inverted. channel configuration register 3 (read/write) value after reset: 00 h pre1, pre0 number of preamble repetition if preamble transmission is initiated, the preamble defined via register pre is transmitted 00 1 times 01 2 times 10 4 times 11 8 times. 70 ccr3 pre1 pre0 ept radd crl rcrc xcrc psd (offset: 2f)
sab 82538 saf 82538 hdlc mode semiconductor group 135 ept enable preamble transmission this bit enables transmission of a preamble. the preamble is started after interframe timefill transmission has been stopped and a new frame is to be transmitted. the preamble consists of an 8-bit pattern repeated a number of times. the pattern is defined via register pre, the number of repetitions is selected by bits pre0 and pre1. note: the shared flag feature is not influenced by preamble transmission. zero bit insertion is disabled during preamble transmission. radd receive address pushed to rfifo if this bit is set to 1, the received hdlc address information (1 or 2 bytes, depending on the address mode selected via mode.adm) is pushed to rfifo. this function is applicable in auto mode, non-auto mode and transparent mode 1. crl crc reset level this bit defines the initialization for the internal receive and transmit crc generators: 0 initialized to (ffff)ffff h . default value for most hdlc/sdlc applications. 1 initialized to (0000)0000 h . rcrc receive crc on/off only applicable in non-auto mode and transparent mode 0. if this bit is set to 1, the received crc checksum will be written to rfifo (crc-ccitt: 2 bytes; crc-32: 4 bytes). the checksum, consisting of the 2 (or 4) last bytes in the received frame, is followed in the rfifo by the status information byte (contents of register rsta). the received crc checksum will additionally be checked for correctness. if non-auto mode is selected, the limits for valid frame check are modified ( refer to rsta.vfr ). xcrc transmit crc on/off if this bit is set to 1, the crc checksum will not be generated internally. it has to be written as the last two or four bytes in the transmit fifo (xfifo). the transmitted frame will be closed automatically with a closing flag. note: the escc8 does not check whether the length of the frame, i.e. the number of bytes to be transmitted makes sense or not.
sab 82538 saf 82538 hdlc mode semiconductor group 136 psd dpll phase shift disable only applicable in the case of nrz and nrzi encoding. if this bit is set to 1, the phase shift function of the dpll is disabled. in this case the windows for phase adjustment are extended. time-slot assignment register transmit (write) this register is only used in clock mode 5! value after reset: 00 h tsnx time-slot number transmit selects one of up 64 possible timeslots (00 h C3f h ) in which data is transmitted. the number of bits per timeslot can be programmed via xccr. xcs2, xcs1 transmit clock shift, bit 2-1 together with bit xcs0 in ccr2, transmit clock shift can be adjusted. time-slot assignment register receive (write) this register is only used in clock mode 5! value after reset: 00 h tsnr time-slot number receive defines one of up to 64 possible time-slots (00 h -3f h ) in which data is received. the number of bits per time-slot can be programmed via rccr. rcs2, rcs1 receive clock shift, bit 2-1 together with bit rcs0 in ccr2, the receive clock shift can be adjusted. 70 tsax tsnx xcs2 xcs1 (offset: 30) 70 tsar tsnr rcs2 rcs1 (offset: 31)
sab 82538 saf 82538 hdlc mode semiconductor group 137 transmit channel capacity register (write) this register is only used in clock mode 5! value after reset: 00 h xbc7 C xbc0 transmit bit number count, bit 7-0 defines the number of bits to be transmitted within a time-slot: number of bits = xbc + 1 (1 256 bits/time-slot). receive channel capacity register (write) this register is only used in clock mode 5! value after reset: 00 h rbc7 C rbc0 receive bit count, bit 7-0 defines the number of bits to be received within a time-slot: number of bits = rbc + 1 (1 256 bits/time-slot). version status register (read) cd carrier detect this bit reflects the state of the cd pin. 1 cd active 0 cd inactive dpla dpll asynchronous this bit is only valid when the receive clock is supplied by the dpll and fm0, fm1 or manchester data encoding is selected. it is set when the dpll has lost synchronization. reception is disabled (receiver aborted) until synchronization has been regained. additionally, transmission is interrupted, too, if the transmit clock is derived from the dpll (same effect as the deactivation of pin cts). 70 xccr xbc7 xbc0 (offset: 32) 70 rccr rbc7 rbc0 (offset: 33) 70 vstr cd dpla 0 0 vn3 vn0 (offset: 34)
sab 82538 saf 82538 hdlc mode semiconductor group 138 vn3 C vn0 version number of chip 0 version 1 1 version 2 baud rate generator register (write) br7 C br0 baud rate, bit 7-0 together with bits br9, br8 of ccr2, determines the division factor of the baud rate generator. in terms of the value n programmed in br9 - br0 ( n = 0 1023), the division factor k is: k = ( n + 1) 2 receive length check register (write) rc receive check (on/off) 0 receive length check feature disabled 1 receive length check feature enabled rl6 C rl0 receive length the maximum receive length after which data reception is suspended can be programmed here. the receive length is (rl + 1) 32 bytes, where rl is the value programmed via rl6-0. a frame exceeding this length is treated as if it was aborted by the opposite station (rme interrupt, rab bit set). in this case, the receive byte count (rbch, rbcl) is greater than the programmed receive length. 70 bgr br7 br0 (offset: 34) 70 rlcr rc rl6 rl0 (offset: 35)
sab 82538 saf 82538 hdlc mode semiconductor group 139 address mask low (write) (version 2 upwards) value after reset: 00 h the receive address low byte (ral1) can be masked by setting corresponding bits in this mask register to allow extended broadcast address recognition. this feature is applicable in all operating modes with address recognition. the function is disabled if all bits of this register are set to zero (reset value). address mask high (write) (version 2 upwards) value after reset: 00 h the function is similar to aml but with respect to register rah1. global interrupt status register (read) value after reset: 00 h this status register points to pending C channel assigned interrupts (isr0_x, isr1_x) C universal port interrupts (pisa..d). gis is accessible via eight channel addresses (038 h to 1f8 h ). pia, pid port interrupt indication these status bits point to pending interrupts in corresponding port interrupt status registers pisapisd. they may be set independently from channel assigned interrupts. 70 aml aml7 aml0 (offset: 36) 70 amh amh7 amh0 (offset: 37) 70 gis pia pib pic pid cii cn2 cn1 cn0 (038/078/0b8/0f8) (138/178/1b8/1f8)
sab 82538 saf 82538 hdlc mode semiconductor group 140 cii channel interrupt indication set if at least one interrupt source of any channel is active. cn2 C cn0 channel number (0..7) if at least one interrupt source is active (bit cii is set), these bits point to the channel with currently highest source priority. refer to chapter 2.2.3 for detailed description of the priority structure. contents of register gis are frozen after every input acknowledge cycle. C after the first read access to gis after the interrupt vector has been output, C after every read access to anyone of the channel assigned interrupt status registers, C during every inta cycle. interrupt vector address (write) value after reset: 00 h note: unused bits have to be set to logical 0. iva is accessible via eight channel addresses (38 h to 1f8 h ). version 2 upward provides dynamic adjustment of channel priorities by programming the highest priority channel. selection of the highest priority channel is done with every write access to iva in conjunction with the channel assigned iva register address: iva register address: highest priority channel 38 h 0 78 h 1 b8 h 2 f8 h 3 138 h 4 178h 5 1b8h 6 1f8h 7 the priority level becomes valid with the end of the write access to the iva register (rising edge of wr or ds, whichever applies) and remains stable until a new write access to this register occurs. 70 iva t7 t6 t5 t4 t3 t2 rot eda (038/078/0b8/0f8) (138/178/1b8/1f8)
sab 82538 saf 82538 hdlc mode semiconductor group 141 t7 C t6 device address these bits define the value of bits 6 and 7 of the interrupt vector which is sent out on the data bus (d0 d7) during the interrupt acknowledge cycle. t5 device address version 1: device address this bit defines the value of bit 5 of the interrupt vector which is sent out on the data bus (d0 d7) during the interrupt acknowledge cycle. version 2: device address extension in interrupt vector mode 2 (bit eda set) this bit defines the value of bit 5 of the interrupt vector which is sent out on the data bus (d0 d7) during the interrupt acknowledge cycle. t4 C t2 device address extension in interrupt vector mode 2 (bit eda set) these bits define the value of bits 2 to 4 of the interrupt vector which is sent out on the data bus (d0 d7) during the interrupt acknowledge cycle. rot rotating interrupt priority (version 2 upward) version 1: this bit is unused and has to be set to logical 0. version 2: 0 fixed interrupt priority the relative order of the interrupt priority level assigned to the channels is fixed ( refer to chapter 2.3.1 ). 1 rotating interrupt priority the interrupt priority level will be adjusted after an interrupt has been serviced. together with bit ipc.rotm the interrupt priority mode is selected. ipc.rotm = 0: the priority level of all 8 serial channels are adjusted. ipc.rotm = 1: the priority level of only 7 channels are adjusted while one channel is fixed. eda extended device address if set, bits 2 to 5 (version 1: bits 2 to 4) of the generated interrupt vector contain the device address extension t2..t5 (version 1: t2..t4) instead of the channel number. for detailed information refer to chapter 2.2.3 .
sab 82538 saf 82538 hdlc mode semiconductor group 142 interrupt port configuration (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. ipc is accessible via eight channel addresses (039 h to 1f9 h ). vis masked interrupts visible (version 2 upward) 0 masked interrupt status bits are not visible. 1 masked interrupt status bits are visible. rotm rotating interrupt priority mode (version 2 upward) together with bit iva.rot the interrupt priority mode is selected. 0 with iva.rot = 1 the priorities of all 8 serial channels are rotated cyclically after an interrupt has been serviced. the channel last serviced is assigned the lowest priority of all ( refer to chapter 2.2.3.1. ). 1 with iva.rot = 0 the priority adjustment is performed only on 7 channels while one channel is fixed to highest priority level ( refer to chapter 2.2.3.1 ). sla2 C sla0 slave address only used in slave cascading mode (refer to casm). casm cascading mode 0 slave cascading mode pins ie0, ie1 and ie2 are used as inputs. interrupt acknowledge is accepted if an interrupt signal has been generated and the values on pins ie0, ie1 and ie2 correspond to the programmed values in sla0, sla1 and sla2 (slave address). 1 daisy chaining mode pin ie0 as interrupt enable output and pin ie1 as interrupt enable input are used for building a daisy chain. pin ie2 is not used. interrupt acknowledge is accepted if an interrupt signal has been generated and interrupt enable input ie1 is active high during a subsequent inta cycle(s). if pin int goes active, interrupt enable output ie0 is immediately set low. 70 ipc vis rotm sla2 sla1 sla0 casm ic1 ic0 (039/079/0b9/0f9) (139/179/1b9/1f9)
sab 82538 saf 82538 hdlc mode semiconductor group 143 ic1, ic0 interrupt port configuration these bits define the function of the interrupt output stage (pin int): interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. additionally, rme and rpf are reset when the corresponding interrupt vector is output. note: if bit ipc.vis is set to 1, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. rme receive message end one complete message of length less than 32 bytes, or the last part of a frame at least 32 bytes long is stored in the receive fifo, including the status byte. the complete message length can be determined reading the rbch, rbcl registers, the number of bytes currently stored in rfifo is given by rbc4C0. additional information is available in the rsta register. rfs receive frame start this is an early receiver interrupt activated after the start of a valid frame has been detected, i.e. after an address match (in operation modes providing address recognition), or after the opening flag (transparent mode 0) is detected, delayed by two bytes. after an rfs interrupt, the contents of rhcr ral1 rsta - bits 3-0 are valid and can be read by the cpu. ioc1 ioc0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high 70 isr0 rme rfs rsc pce plla cdsc rfo rpf (offset: 3a)
sab 82538 saf 82538 hdlc mode semiconductor group 144 rsc receive status change (significant in auto-mode only) a status change (receiver ready/receiver not ready) of the remote station has been detected by receiving a rr/rnr supervisory frame. the actual status can be read from the star register (rrnr bit). pce protocol error (significant in auto-mode only) the escc8 has detected a protocol error, i.e. it has received C an s- or i-frame with incorrect n (r) C an s-frame containing an i-field. plla dpll asynchronous this bit is only valid when the receive clock is supplied by the dpll and fm0, fm1 or manchester data encoding is selected. it is set when the dpll has lost synchronization. reception is disabled (receiver aborted) until synchronization has been regained. additionally, transmission is also interrupted if the transmit clock is derived from the dpll. cdsc carrier detect status change indicates that a state transition has occurred on cd. the actual state can be read from the vstr register. rfo receive frame overflow at least one complete frame was lost because no storage space was available in the rfifo. this interrupt can be used for statistical purposes and indicates that the cpu does not respond quickly enough to an rpf or rme interrupt. rpf receive pool full 32 bytes of a frame have arrived in the receive fifo. the frame is not yet completely received. note: this interrupt is only generated in interrupt mode.
sab 82538 saf 82538 hdlc mode semiconductor group 145 interrupt status register 1 (read) all bits are reset when isr1 is read. additionally, xpr is reset when the corresponding interrupt vector is output. note: if bit ipc.vis is set to 1, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. eop... end of poll sequence detected only valid if sdlc loop mode is selected. it is set if an eop sequence has been received. olp/rdo... on loop only valid if sdlc loop mode is selected. it is set in response to a go on loop command, but not before an eop sequence has been received. it is also set when returning from the active on loop state. all incoming bits on r d are reflected onto t d with one bit delay. receive data overflow not applicable in sdlc loop mode this interrupt status is an early warning that data has been lost. it is classified as group 7 or group 8 interrupt. even when this interrupt status is generated, the frame continues to be received when space in the rfifo is available again. note: whereas the bit rsta.rdo in the frame status byte indicates whether an overflow occurred when receiving the frame currently accessed in the rfifo, the isr1.rdo interrupt status is generated as soon as an overflow occurs and does not necessarily pertain to the frame currently accessed by the processor or the dma controller. aolp/alls... active on loop only valid if sdlc loop mode is selected. it is set in response to a go active on loop command, but not before an eop sequence has been received. t d is disconnected from r d and transmission of flags or data is started. all sent only valid if sdlc loop mode is not selected. 70 isr1 eop olp/ rdo aolp/ alls xdu/ exe tin csc xmr xpr (offset: 3b)
sab 82538 saf 82538 hdlc mode semiconductor group 146 this bit is set C if the last bit of the current frame is completely sent out on t d and xfifo is empty (non-auto mode, transparent modes). C if an i-frame is completely sent out on t d and a positive acknowledgment has been received (auto mode). C in auto-mode, if an i-frame has been sent and a timer interrupt (tin) is generated because the internal timer expires before an acknowledgment is received: in this case alls is generated one clock period after (tin). xdu/exe... transmit data underrun/extended transmission end transmitted frame was terminated with an abort sequence because no data was available for transmission in xfifo and no xme was issued (interrupt mode) or dma request was not satisfied in time (dma mode). note: transmitter and xfifo are reset and deactivated if this condition occurs. they are re-activated not before this interrupt status register has been read. thus, xdu should not be masked via register imr1. in extended transparent mode, this bit indicates the transmission-end condition (exe). tin... timer interrupt the internal timer and repeat counter has expired (see also description of timr register). csc... clear to send status change indicates that a state transition has occurred on cts. the actual state can be read from star register (cts bit). xmr... transmit message repeat the transmission of the last frame has to be repeated because C the escc8 has received a negative acknowledgment to an i-frame in auto-mode, or C a collision has occurred after at least one fifo block of data has been completely transmitted, and thus an automatic re-transmission cannot be attempted, or C cts (transmission enable) has been withdrawn after at least one fifo block of data has been transmitted and the frame has not been completed. note: for easier recovery in the case of a collision, xfifo should not contain data of more than one frame. the use of alls interrupt is therefore recommended.
sab 82538 saf 82538 hdlc mode semiconductor group 147 in case an xmr interrupt has occured, an alls interrupt is generated one clock period later automatically. xpr... transmit pool ready a data block of up to 32 bytes can be written to the transmit fifo. xpr enables the fastest access to xfifo. it has to be used for transmission of long frames, back-to-back frames or frames with shared flags. however, starting transmission of a new frame should be initiated after alls interrupt instead of xpr C in auto mode C in bus configurations C if contents of xfifo have to be unique, e.g. for automatic repetition of the last frame in case of bus collisions or cts control (see also xmr interrupt). note: it is not possible to send transparent, or i-frames when a xmr or xdu interrupt remains unacknowledged. interrupt mask register 0, 1 (write) value after reset: ff h , ff h each interrupt source can generate an interrupt signal at port int (characteristics of the output stage are defined via register ipc). a 1 in a bit position of imr0 or imr1 sets the mask active for the interrupt status in isr0 or isr1. masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit ipc.vis is set to 0 C be displayed in the interrupt status register if bit ipc.vis is set to 1. note: after reset, all interrupts are dis abled. 70 imr0 rme rfs rsc pce plla cdsc rfo rpf (offset: 3a) imr1 eop olp/ rdo aolp/ alls xdu/ exe tin csc xmr xpr (offset: 3b)
sab 82538 saf 82538 hdlc mode semiconductor group 148 port value register port a...d (read/write) note: unused bits have to be set to logical 0. each pvr register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin with the same number (e.g. pvra.0 to port pin pa0). read access pvr shows the value of all pins (input and output). input values can be separated via software by and-ing pcr and pvr. write access pvr accepts values for all output pins (defined via pcr). values written to input pin locations are ignored. 70 pvra pvr7 pvr0 (03c/07c) pvrb pvr7 pvr0 (0bc/0fc) pvrc pvr7 pvr0 (13c/17c) pvrd 0 0 0 0 pvr3 pvr0 (1bc/1fc)
sab 82538 saf 82538 hdlc mode semiconductor group 149 port interrupt status register port a...d (read) each pis register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin with the same number (e.g. pisa.0 to pin pa0). bit pisn is set and an interrupt is generated on int if C the corresponding universal port pin pn is defined as input via register pcr and C the interrupt source is enabled by resetting the corresponding interrupt mask pimn in register pim and C a state transition has occurred on pin pn. for definite detection of a real state transition, pulse width should not be shorter than 20 ns. note: bits pisn are reset when register pis is read. masked interrupts are not normally indicated when pis is read. instead, they remain internally stored and pending. a pending interrupt is generated when the corresponding mask bit is reset to zero. however, if bit ipc.vis is set to 1, interrupt statuses in pis may be flagged although they are masked via register pim. these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. if more than one consecutive state transitions occur on the same pin before the pis register is read, only one interrupt request will be generated. 70 pisa pis7 pis0 (03d/07d) pisb pis7 pis0 (0bd/0fd) pisc pis7 pis0 (13d/17d) pisd 0 0 0 0 pis3 pis0 (1bd/1fd)
sab 82538 saf 82538 hdlc mode semiconductor group 150 port interrupt mask register port a...d (write) value after reset: ff h note: unused bits have to be set to logical 0. each pim register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin and to the bits of register pis with the same number (e.g. pima0 to pin pa0). 0 interrupt source is enabled. 1 interrupt source is disabled. a 1 in a bit position of pim sets the mask active for the interrupt status in pis. masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit ipc.vis is set to 0 C be displayed in the interrupt status register if bit ipc.vis is set to 1. refer to description of register pis. note: after reset, all interrupt sources are dis abled. 70 pima pim7 pim0 (03d/07d) pimb pim7 pim0 (0bd/0fd) pimc pim7 pim0 (13d/17d) pimd 0 0 0 0 pim3 pim0 (1bd/1fd)
sab 82538 saf 82538 hdlc mode semiconductor group 151 port configuration register port a...d (read/write) value after reset: ff h note: unused bits have to be set to logical 0. each pcr register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin with the same number (e.g. pcra.0 to pin pa0). if bit pcrn (n = 0...7) is set to 0 pin pn is defined as output. 1 pin pn is defined as input. note: after reset, all pins of the universal port are defined as in puts. 70 pcra pcr7 pcr) (03e/07e) pcrb pcr7 pcr0 (0be/0fe) pcrc pcr7 pcr0 (13e/17e) pcrd 0 0 0 0 pcr3 pcr0 (1be/1fe)
sab 82538 saf 82538 hdlc mode semiconductor group 152 channel configuration register 4 (read/write) (version 2 upwards) value after reset: 00 h note: unused bits have to be set to logical 0. rft1, rft0 rfifo threshold level the size of the accessible part of rfifo can be determined by programming these bits. the number of valid bytes after an rpf interrupt is given in the following table: the value of rft 1,0 can be changed dynamically C if reception is not running (recommended: receiver is disabled by setting mode.rac to 0), or C after rme interrupt has been generated, but before the command cmdr.rmc is issued (dma controlled data transfer), or C after the current data block has been read, but before the command cmdr.rmc is issued (interrupt controlled data transfer). see note . note: it is seen that changing the value of rft1,0 is possible even during the reception of one frame. the total length of the received frame can be always read directly in rbcl, rbch after an rpf interrupt, except when the threshold is increased during reception of that frame. the real length can then be inferred by noting which bit positions in rbcl are reset by an rmc command ( see table below ): 70 ccr4 0 00000 rft1 rft0 (offset: 3f) rft1 rft0 size of accessible part of rfifo 0 0 1 1 0 1 0 1 32 bytes (reset value) 16 bytes 4 bytes 2 bytes rft1 rft0 bit positions in rbcl reset by a cmdr.rmc command 0 0 1 1 0 1 0 1 rbc4 . 0 rbc3 0 rbc1,0 rbc0
semiconductor group 153 sab 82538 saf 82538 async mode 4.2 status/control registers in async mode 4.2.1 register addresses table 10 register addresses in async mode *) all channel assigned addresses enable access to the same register(s) note: read access to unused register addresses: value should be ignored, write access to unused register addresses: should be avoided, or set to 00 h . address (a8 a0) register channel 0 1 2 3 4 5 6 7 read write 000 01f 040 05f 080 09f 0c0 0df 100 11f 140 15f 180 19f 1c0 1df rfifo xfifo 020 060 0a0 0e0 120 160 1a0 1e0 star cmdr 021 061 0a1 0e1 121 161 1a1 1e1 022 062 0a2 0e2 122 162 1a2 1e2 mode 023 063 0a3 0e3 123 163 1a3 1e3 timr 024 064 0a4 0e4 124 164 1a4 1e4 xon 025 065 0a5 0e5 125 165 1a5 1e5 xoff 026 066 0a6 0e6 126 166 1a6 1e6 tcr 027 067 0a7 0e7 127 167 1a7 1e7 dafo 028 068 0a8 0e8 128 168 1a8 1e8 rfc 029 069 0a9 0e9 129 169 1a9 1e9 02a 06a 0aa 0ea 12a 16a 1aa 1ea rbcl xbcl 02b 06b 0ab 0eb 12b 16b 1ab 1eb rbch xbch 02c 06c 0ac 0ec 12c 16c 1ac 1ec ccr0 02d 06d 0ad 0ed 12d 16d 1ad 1ed ccr1 02e 06e 0ae 0ee 12e 16e 1ae 1ee ccr2 02f 06f 0af 0ef 12f 16f 1af 1ef ccr3 030 070 0b0 0f0 130 170 1b0 1f0 tsax 031 071 0b1 0f1 131 171 1b1 1f1 tsar 032 072 0b2 0f2 132 172 1b2 1f2 xccr 033 073 0b3 0f3 133 173 1b3 1f3 rccr 034 074 0b4 0f4 134 174 1b4 1f4 vstr bgr 035 075 0b5 0f5 135 175 1b5 1f5 tic 036 076 0b6 0f6 136 176 1b6 1f6 mxn 037 077 0b7 0f7 137 177 1b7 1f7 mxf 038, 078, 0b8, 0f8, 138, 178, 1b8, 1f8 gis *) iva *) 039, 079, 0b9, 0f9, 139, 179, 1b9, 1f9 ipc *) 03a 07a 0ba 0fa 13a 17a 1ba 1fa isr0 imr0 03b 07b 0bb 0fb 13b 17b 1bb 1fb isr1 imr1 03c, 07c 0bc, 0fc 13c, 17c 1bc, 1fc pvrad 03d, 07d 0bd, 0fd 13d, 17d 1bd, 1fd pisad pimad 03e, 07e 0be, 0fe 13e, 17e 1be, 1fe pcrad 03f, 07f 0bf, 0ff 13f, 17f 1bf, 1ff
semiconductor group 154 sab 82538 saf 82538 async mode 4.2.2 register definitions receive fifo (read) rfifo (offset: 001f) received data stored in rfifo (lsb is received first) can be organized in one of two selectable ways ( refer to figure 49 ): C pure data up to a character length of 8 bits (incl. optional parity) C additionally, one status byte per character with information about parity (if enabled), parity error and framing error. reading data from rfifo can be done in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. figure 49 organization of rfifo
semiconductor group 155 sab 82538 saf 82538 async mode interrupt controlled data transfer (interrupt mode) selected if dma bit in xbch is reset. up to 32 bytes/16 words of received data can be read from the rfifo following a rpf or a tcd interrupt depending on the selected rfifo mode (refer to rfc register): rpf interrupt: a fixed number of bytes/words (programmed threshold level rfth0, 1) has to be read by the cpu. tcd interrupt: termination character detected. the received data stream is monitored for termination character (programmable via register tcr). the number of valid bytes in rfifo is determined by reading the rbcl register. if necessary, the cpu can access the rfifo by issuing rfifo read command (cmdr.rfrd) before threshold level or the termination condition is reached. the number of valid bytes is determined by reading the rbcl register. additional information: star.rfne: rfifo not empty. dma controlled data transfer (dma mode) selected if dma bit in xbch is set. if the rfifo contains the number of bytes/words defined via the threshold level, the escc8 autonomously requests a dma block data transfer by dma by activating the drrn line until the last valid data is read (the ddrn line remains active up to the beginning of the last read cycle). this forces the dma controller to continuously perform bus cycles till all data is transferred from the escc8 to the system memory (level triggered transfer mode of dma controller). if the end condition (tcd) is reached, the same procedure as above is performed. drrn is activated until the termination character is transferred. a tcd interrupt is issued after the last data has been transferred. generation of further dma requests is blocked until tcd interrupt has been acknowledged by issuing an rmc command. the valid byte count of the last block can be determined by reading the rbcl register following the tcd interrupt. note: addresses within the 32-byte address space of the fifos point all to the same byte/word, i.e. current data can be accessed with any address within the valid scope. transmit fifo (write) xfifo (offset: 001f) writing data to xfifo can be in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is transmitted first. interrupt mode selected if dma bit in xbch is reset. up to 32 bytes/16 words of transmit data can be written to the xfifo following an xpr interrupt.
semiconductor group 156 sab 82538 saf 82538 async mode dma mode selected if dma bit in xbch is set. prior to any data transfer, the actual byte count to be transmitted must be written to the xbch, xbcl registers by the user. correct transmission of data in the case of word access and of an odd number of bytes specified in xbch, xbcl is guaranteed. if data transfer is then initiated via the cmdr register (command xf), the escc8 autonomously requests the correct amount of block data transfers (n bw + rest; bw = 32, 16; n = 0, 1,). note: addresses within the 32-byte address space of the fifo all point to the same byte/word, i.e. current data can be accessed with any address within the valid range. status register (read) xdov transmit data overflow more than 32 bytes have been written to the xfifo. this bit is reset by: C a transmitter reset command xres C or when all bytes in the accessible half of the xfifo have been moved in the inacessible half. xfw transmit fifo write enable data can be written to the xfifo. rfne rfifo not empty this bit is set if the accessible part of rfifo holds at least one valid byte. fcs flow control status if in-band flow control is enabled via bit mode.flon, this status bit indicates the current state of the transmitter: 0 the transmitter is in xon state, i.e. transmission is enabled or running. 1 the transmitter is in xoff state, i.e. transmission is stopped and disabled until an xon character is detected by the receiver. 70 star xdov xfw rfne fcs tec cec cts 0 (offset: 20)
semiconductor group 157 sab 82538 saf 82538 async mode tec tic executing this status bit indicates that transmission instruction of currently programmed tic (transmit immediate character) is accepted but not completely executed. further access to register tic is only allowed after star.tec has been reset by the escc8. note: status flag tec is set immediately with the write access to register tic. it remains active until the transmitter of escc8 is able to start transmission of currently programmed tic. best case: tec remains set for at most 2.5 clock periods (transmit clock or master clock, depending of the selected mode) if transmission of the programmed tic character can be started immediately. the function of register tic and status flag tec is independent of whether flow control is enabled or not. cec command executing 0 no command is currently being executed, the cmdr register can be written to. 1 a command (written previously to cmdr) is currently being executed, no further command can be temporarily written in cmdr register. note: cec will be active at most 2.5 transmit clock periods. if the escc8 is in power down mode cec will stay active. cts clear to send state this bit indicates the state of the cts pin. 0 cts is inactive (high) 1 cts is active (low)
semiconductor group 158 sab 82538 saf 82538 async mode command register (write) value after reset: 00 h note: unused bits have to be set to logical 0. the maximum time between writing to the cmdr register and the execution of the command is 2.5 clock cycles. therefore, if the cpu operates with a very high clock rate in comparison with the escc8s clock, it is recommended that the cec bit of the star register be checked before writing to the cmdr register to avoid any loss of commands. rmc receive message complete confirmation from cpu to escc8 that the current data block has been fetched following a rpf or tcd interrupt or following a user initiated read access in conjunction with the rfifo read command rfrd; the occupied space in the rfifo can be released. note: in dma mode, this command has to be issued after a tcd interrupt in order to enable the generation of further receiver dma requests. rres receiver reset all data in rfifo and async receiver is deleted. rfrd receive fifo read enable the cpu can have access to rfifo by issuing the rfrd command before threshold level or the end condition (tcd) are fulfilled. after issuing the rfrd command the cpu has to wait for tcd interrupt, before reading rbc and rfifo. the number of valid bytes is determined by reading the rbcl register. sti start timer the internal timer is started. note: the timer is stopped by rewriting the timr register after start. xf transmit frame l interrupt mode after having written up to 32 bytes/16 words to the xfifo, this command initiates the transmission of data. l dma mode after having written the amount of data to be transmitted to the xbch, xbcl registers, this command initiates the data transfer from system 70 cmdr rmc rres rfrd sti xf 0 0 xres (offset: 20)
semiconductor group 159 sab 82538 saf 82538 async mode memory to escc8 by dma. serial data transmission starts as soon as 32 bytes/16 words are stored in the xfifo or the transmit byte counter value is reached. xres transmitter reset xfifo is cleared of any data and idle (logical 1s) is transmitted. this command can be used by the cpu to abort current data transmission. in response to xres an xpr interrupt is generated. mode register (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. flon flow control on the in-band flow control is activated via this bit: 0 no further action is automatically taken by the escc8. however, recognition of an xon or an xoff character (defined via registers xon and xoff) causes always a corresponding maskable interrupt status to be generated ( refer to register isr1 ). 1 the reception of an xoff character (defined via register xoff) automatically turns off the transmitter after the currently transmitted character (if any) has been completely shifted out (xoff state). the reception of an xon character (defined via register xon) automatically makes the transmitter resume transmitting (xon state). rac receiver active switches the receiver to operational or inoperational state. 0 receiver inactive 1 receiver active 70 mode 0 0 0 flon rac rts trs tlp (offset: 22)
semiconductor group 160 sab 82538 saf 82538 async mode rts request to send defines the state and control of rts pin. 0 the rts pin is controlled by the escc8 autonomously. rts is activated when data transmission starts and deactivated when transmission is completed. 1 the rts pin is controlled by the cpu. if this bit is set, the rts pin is activated immediately and remains active till this bit is reset. trs timer resolution selects the resolution of the internal timer (factor k , see description of timr register): 0 k = 32 768 1 k = 512 tlp test loop input and output of the async channels are internally connected. (e.g. transmitter channel 0 - receiver channel 0) timer register (read/write) value (5 bits) sets the time period t1 as follows: t 1 = k (value + 1) tcp where C k is the timer resolution factor which is either 32 768 or 512 clock cycles dependent on the programming of trs bit in mode. C tcp is the clock period of transmit data. cnt (3 bits) cnt plus value determine the time period t 2 after which a timer interrupt will be generated. the time period t 2 is t 2 = 32 k cnt tcp + t 1 . if cnt is set to 7, a timer interrupt is periodically generated after the expiration of t 1 . 70 timr cnt value (offset: 23)
semiconductor group 161 sab 82538 saf 82538 async mode xon character (read/write) value after reset: 00 h this register is used to specify the xon character. it can be used in conjunction with the interrupt status isr1.xon for automatic in-band flow control (if mode.flon = 0). the number of significant bits is determined by the programmed character length (right justified). a received character is considered to be recognized as a valid xon character C if it is correctly framed (correct length), C if its bits match the (unmasked) ones in the xon register over the programmed character length, C if it has correct parity (if applicable). received xon characters are always stored in the receive fifo, similar to other characters. xoff character (read/write) value after reset: 00 h this register is used to specify the xoff character. it can be used in conjunction with the interrupt status isr1.xoff for automatic in-band flow control (if mode.flon = 1), or as a special character compare register for other purposes (if mode.flon = 0). the number of significant bits is determined by the programmed character length (right justified). a received character is considered to be recognized as a valid xoff character C if it is correctly framed (correct length), C if its bits match the (unmasked) ones in the xoff register over the programmed character length, C if it has correct parity (if applicable). received xoff characters are always stored in the receive fifo, similar to other characters. 70 xon xon7 xon0 (offset: 24) 70 xoff xof7 xof0 (offset: 25)
semiconductor group 162 sab 82538 saf 82538 async mode termination character register (read/write) value after reset: 00 h tcr7Ctcr0 termination character if enabled via register rfc the received data stream is monitored for the occurrence of a programmed termination character. when such a character is found, an interrupt is issued if enabled via mask register imr0. the number of valid bytes in the rfifo up to and including the termination character is determined by reading the rbcl register. note: if selected character length is less than eight bits, leading (unused) bits of tcr have to be set to 0. data format (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. xbrk transmit break 0 normal operation for data transmission. 1 this command forces the t d pin to go low, regardless of any data being transmitted at this time. this command is executed immediately (with the next rising edge of transmit clock) and the transmitter is disabled. the current character is lost. however, the contents of xfifo are still available and are sent out as soon as this bit is reset. to avoid this the transmit reset command xres should be issued. if xbrk is still set when xres is issued the break signal on t d stays active. 70 tcr tcr7 tcr0 (offset: 26) 70 dafo 0 xbrk stop par1 par0 pare chl1 chl0 (offset: 27)
semiconductor group 163 sab 82538 saf 82538 async mode stop stop bit this bit defines the number of stop bits generated by the transmitter: 01 stop bit. 12 stop bits. par1, par0 parity format if parity check/generation is enabled by setting pare, these bits define the parity type: 00 space (0) 01 odd parity 10 even parity 11 mark (1) the received parity bit is stored in rfifo C as leading bit immediately preceding the character if character length is 5 to 7 bits and rfc.dps is set to 0, and as lsb of the status byte pertaining to the character if the corresponding rfifo data format is enabled. C as lsb of the status byte pertaining to the character if character length is 8 bits and the corresponding rfifo data format is enabled. parity error is indicated in the msb of the status byte pertaining to the character, if enabled. additionally, a parity error interrupt can be generated. pare parity enable 0 parity check/generation disabled 1 parity check/generation enabled chl1Cchl0 character length these bits define the length of received and transmitted characters, excluding optional parity: 00 8 bit 01 7 bit 10 6 bit 11 5 bit
semiconductor group 164 sab 82538 saf 82538 async mode rfifo control register (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. dps disable parity storage only valid if parity check/generation is enabled via dafo.pare and character length is less than 8 bits. 0 the parity bit is stored 1 the parity bit is not stored in the data byte of rfifo. note: the parity bit is always stored in the status byte. rfdf rfifo data format 0 only data bytes (character plus optional parity up to 8 bit) are stored. 1 additionally to every data byte, an attached status byte is stored. fe : framing error pe : parity error p : parity bit (p): can be disabled via bit dps 70 rfc 0 dps 0 rfdf rfth1 rfth0 0 tcde (offset: 28) rfdf = 0 rfdf = 1 C character 5 C 8 bit or C character 5 C 7(8)* bit + parity * : parity bit is lost C character 5 C 8 bit + status or C character 5 C 7(8)* bit + parity + status * : parity bit is in status byte 74 0 data byte (p) char 74 0 data byte (p) char 76 0 status byte pe fe p
semiconductor group 165 sab 82538 saf 82538 async mode rfth1, rfth0 rfifo threshold level these bits define the level up to which rfifo is filled with valid data: d: data byte s: status byte if the threshold level is reached, the rpf interrupt is generated if enabled. after rpf is generated, the contents of rfifo (rfth bytes) can be read by the cpu. to indicate that this rfifo pool can be released, an rmc command has to be issued. tcde termination character detection enable when this bit is set, the received data stream is monitored for termination character (tcr register). when such a character occurs, the tcd interrupt is generated if enabled via mask register imr0. the number of bytes to be read from rfifo is determined by the value of rbcl. receive byte count low (read) indicates the number of valid bytes available in the accessible part of the rfifo. this register must be read by the cpu following a tcd interrupt. in case of a tcd interrupt the number of valid bytes in the accessible part of the rfifo can be evaluated by and-ing the contents of rbcl with: threshold level (bytes) C 1. rbc is reset with rmc after preceeding tcd interrupt. in case of rpf interrupt rbc is incremented by threshold level (bytes). rfth1, 0 threshold level (bytes) rfdf = 0 rfdf = 1 00 01 10 11 1 ( 1d) 4 ( 4d) 16 (16d) 32 (32d) 2 ( 1d + 1s) 4 ( 2d + 2s) 16 ( 8d + 8s) 32 (16d + 16s) 70 rbcl rbc7 rbc0 (offset: 2a) threshold level mask 4 16 32 03 h 0f h 1f h
semiconductor group 166 sab 82538 saf 82538 async mode transmit byte count low (write) together with xbch (bits xbc11xbc8) this register is used in dma mode only, to program the length (14096 bytes) of the next data block to be transmitted. in terms of the value xbc, programmed in xbc11xbc0 (xbc = 04095), the length of the block in number of bytes is: length = xbc + 1. this allows the escc8 to request the correct amount of dma cycles after an xf command in cmdr. received byte count high (read) value after reset: 000xxxxx dma, cas these bits represent the read-back value programmed in xbch rbc11C rbc8 receive byte count (most significant bits) no function in async mode. transmit byte count high (write) value after reset: 000xxxxx note: unused bits have to be set to logical 0. dma dma mode selects the data transfer mode of escc8 to/from system memory. 0 interrupt controlled data transfer (interrupt mode). 1 dma controlled data transfer (dma mode). 70 xbcl xbc7 xbc0 (offset: 2a) 70 rbch dma 0 cas 0 rbc11 rbc8 (offset: 2b) see xbch 70 xbch dma 0 cas xc xbc11 xbc8 (offset: 2b)
semiconductor group 167 sab 82538 saf 82538 async mode cas carrier detect auto start when set, a high on the cd pin enables the corresponding receiver and data reception is started. when not set, if not in clock mode 1 or 5, the cd pin can be used as a general input. xc transmit continuously only valid if dma mode is selected. if the xc bit is set, the escc8 continuously requests for transmit data ignoring the transmit byte count programmed via xbch, xbcl. xbc11C xbc8 transmit byte count (most significant bits) valid only if dma mode is selected. together with xbcl (bits xbc7xbc0), determine the number of characters to be transmitted.
semiconductor group 168 sab 82538 saf 82538 async mode channel configuration register 0 (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. pu switches between power up and power down mode 0 power down (standby) 1 power up (active) mce master clock enable if this bit is set to 1, the clock provided via pin xtal1 works as master clock to allow full functionality of the microprocessor interface (access to all status and control registers, dma and interrupt support) independent of the receive and the transmit clocks. the internal oscillator in conjunction with a crystal on xtal1-2 can be used, too. the master clock option is not applicable in clock mode 5. refer to table 5 for more details. note: the internal timers run with the master clock. sc2C sc0 serial port configuration 000 nrz data encoding 001 (not recommended) 010 nrzi data encoding 011 (not recommended) 100 fm0 data encoding 101 fm1 data encoding 110 manchester data encoding 111 (not used) sm1C sm0 serial mode 00 hdlc/sdlc mode 01 sdlc loop mode 10 bisync mode 11 async mode 70 ccr0 pu mce 0 sc2 sc1 sc0 sm1 sm0 (offset: 2c)
semiconductor group 169 sab 82538 saf 82538 async mode channel configuration register 1 (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. ods output driver select defines the function of the transmit data pins (t da, t db) 0 t d pin is an open drain output. 1 t d pin is a push-pull output. bcr bit clock rate this bit is only valid in clock modes not using the dpll (0, 1, 3b, 4, 7b). 0 selects isochronous operation with a bit clock rate = 1. data is sampled once. 1 selects standard asynchronous operation with a bit clock rate = 16. data is sampled 3 times around the nominal bit center. the effective bit value is determined by majority decision. for correct operation, nrz data encoding has to be selected. cm2C cm0 clock mode selects one of 8 different clock modes: 000 clock mode 0 ?? ?? ?? 111 clock mode 7 note: clock mode 5 is only specified for version sab 82538h-10, not for sab 82538h. 70 ccr1 0 0 0 ods bcr cm2 cm0 (offset: 2d)
semiconductor group 170 sab 82538 saf 82538 async mode channel configuration register 2 (read/write) value after reset: 00 h the meaning of the individual bits in ccr2 depends on the clock mode selected via ccr1 as follows: note: unused bits have to be set to logical 0. soc1, soc0 special output control in a bus configuration (selected via ccr0) defines the function of pin rts as follows: 0x rts output is activated during transmission of characters. 10 rts output is always high ( rts disabled). 11 rts indicates the reception of a data frame (active low). in a point-to-point configuration (selected via ccr0) the t d and r d pins may be flipped 0x data is transmitted on t d, received on r d (normal case). 1x data is transmitted on r d, received on t d. br9, br8 baud rate, bit 9-8 high order bits, see description of bgr register. xcs0, rcs0... transmit/receive clock shift, bit 0 together with xcs2, xcs1 (rcs2, rcs1) in tsax (tsar), determines the clock shift relative to the frame synchronization signal of the transmit (receive) time-slot. a clock shift of 0 ... 7 bits is programmable (clock mode 5 only). 70 ccr2 clock mode 0a, 1 soc1 soc0 0 0 0 rwx 0 div (offset: 2e) clock mode 0b, 2, 3, 6, 7 br9 br8 bdf ssel toe rwx 0 div clock mode 4 soc1 soc0 0 0 toe rwx 0 div clock mode 5 soc1 soc0 xcs0 rcs0 toe rwx 0 div
semiconductor group 171 sab 82538 saf 82538 async mode bdf... baud rate division factor 0the division factor of the baud rate generator is set to 1 (constant). 1the division factor is determined by br9 - br0 bits in ccr2 and brg registers. ssel... clock source select selects the clock source in clock modes 0, 2, 3, 6 and 7 ( refer to table 5 ). toe... t clk output enable 0 t clk pin is input 1 t clk pin is switched to output function if applicable to the selected clock mode ( refer to table 5 ). rwx... read/write exchange valid only in dma mode. if this bit is set, the C rd and wr pins are internally exchanged (siemens/intel bus interface) C r/ w pin is inverted in polarity (motorola bus interface) while any dack input is active. this useful feature allows a simple interfacing to the dma controller. note: the rwx bit of all eight channels is ored. div... data inversion only valid if nrz data encoding is selected. data is transmitted and received inverted. channel configuration register 3 (read/write) (version 2 upwards) value after reset: 00 h note: unused bits have to be set to logical 0. psd dpll phase shift disable only applicable in the case of nrz and nrzi encoding. if this bit is set to 1, the phase shift function of the dpll is disabled. in this case the windows for phase adjustment are extended. 70 ccr3 0 000000psd (offset: 2f)
semiconductor group 172 sab 82538 saf 82538 async mode time-slot assignment register transmit (write) this register is only used in clock mode 5! value after reset: 00 h tsnx time-slot number transmit selects one of up 64 possible time-slots (00 h -3f h ) in which data is transmitted. the number of bits per time-slot can be programmed via xccr. xcs2 xcs1 transmit clock shift, bit 2-1 together with bit xcs0 in ccr2, transmit clock shift can be adjusted. time-slot assignment register receive (write) this register is only used in clock mode 5! value after reset: 00 h tsnr time-slot number receive defines one of up to 64 possible time-slots (00 h C 3f h ) in which data is received. the number of bits per time-slot can be programmed via rccr. rcs2C rcs1 receive clock shift, bit 2-1 together with bit rcs0 in ccr2, the receive clock shift can be adjusted. transmit channel capacity register (write) this register is only used in clock mode 5! value after reset: 00 h xbc7C xbc0 transmit bit number count, bit 7-0 defines the number of bits to be transmitted within a time-slot: number of bits = xbc + 1 (1 256 bits/time-slot). 70 tsax tsnx xcs2 xcs1 (offset: 30) 70 tsar tsnr rcs2 rcs1 (offset: 31) 70 xccr xbc7 xbc0 (offset: 32)
semiconductor group 173 sab 82538 saf 82538 async mode receive channel capacity register (write) this register is only used in clock mode 5! value after reset: 00 h rbc7C rbc0 receive bit count, bit 7-0 defines the number of bits to be received within a time-slot: number of bits = rbc + 1 (1256 bits/time-slot). version status register (read) cd carrier detect this bit reflects the state of the cd pin. 1 cd active 0 cd inactive dpla dpll asynchronous this bit is only valid when the receive clock is supplied by the dpll and fm0, fm1 or manchester data encoding is selected. it is set when the dpll has lost synchronization. reception is disabled (idle is inserted) until synchronization has been regained. additionally, transmission is interrupted, too, if the transmit clock is derived from the dpll (same effect as the deactivation of pin cts). vn3C vn0 version number of chip 0 version 1 1 version 2 70 rccr rbc7 rbc0 (offset: 33) 70 vstr cd dpla 0 0 vn3 vn0 (offset: 34)
semiconductor group 174 sab 82538 saf 82538 async mode baud rate generator register (write) br7C br0 baud rate, bits 7-0 together with bits br9, br8 of ccr2, determines the division factor of the baud rate generator. in terms of the value n programmed in br9 - br0 ( n = 01023), the division factor k is: k = ( n + 1) 2 transmit immediate character (write) (version 2 upwards) when a character is written into this register its contents are inserted in the outgoing character stream C immediately upon writing this register by the microprocessor if the transmitter is in idle state. if no further characters (xfifo contents) are to be transmitted, i.e. the transmitter returns to idle state after transmission of tic, an alls (all sent) interrupt will be generated. C after the end of a character currently being transmitted. this does not affect the contents of the xfifo. transmission of characters from xfifo is resumed after the contents of register tic are shifted out. transmission via this register is possible even when the transmitter is in xoff state (however, cts must be low). the tic register is an eight-bit register. the number of significant bits is determined by the programmed character length (right justified). parity value (if programmed) and selected number of stop bits are automatically appended, similar to the characters written in the xfifo. the usage of tic is independent of the flow control, i.e. is not affected by bit mode.flon. to control access to register tic, an additional status bit star.tec (tic executing) is implemented which indicates that transmission instruction of currently programmed tic is accepted but not completely executed. further access to register tic is only allowed if bit star.tec is reset by the escc8. 70 bgr br7 br0 (offset: 34) 70 tic tic7 tic0 (offset: 35)
semiconductor group 175 sab 82538 saf 82538 async mode mask xon character (write) (version 2 upwards) value after reset: 00 h this register is used to masked single bit positions of the xon character. refer to the description of the xon register. the number of significant bits is determined by the programmed character length (right justified). a 1 in the mask register has the effect that no comparison is performed between the corresponding bits in the received characters (dont cares) and the xon register. at reset, the mask register is zeroed, i.e. all bit positions are compared. mask xoff character (write) (version 2 upwards) value after reset: 00 h this register is used to mask single bit positions of the xoff character. refer to the description of the xoff register. the number of significant bits is determined by the programmed character length (right justified). a 1 in the mask register has the effect that no comparison is performed between the corresponding bits in the received characters (dont cares) and the xoff register. at reset, the mask register is zeroed. i.e. all bit positions are compared. 70 mxn mxn7 mxn0 (offset: 36) 70 mxf mxf7 mxf0 (offset: 37)
semiconductor group 176 sab 82538 saf 82538 async mode global interrupt status register (read) value after reset: 00 h this status register points to pending C channel assigned interrupts (isr0_x, isr1_x) C universal port interrupts (pisad). gis is accessible via eight channel addresses (038 h to 1f8 h ). piaC pid port interrupt indication these status bits point to pending interrupts in corresponding port interrupt status registers pisapisd. they may be set independently from channel assigned interrupts. cii channel interrupt indication set if at least one interrupt source of any channel is active. cn2C cn0 channel number (07) if at least one interrupt source is active (bit cii is set), these bits point to the channel with currently highest source priority. refer to chapter 2.2.3 for detailed description of the priority structure. contents of register gis are frozen after every input acknowledge cycle. C after the first read access to gis after the interrupt vector has been output, C after every read access to anyone of the channel assigned interrupt status registers, C during every inta cycle. 70 gis pia pib pic pid cii cn2 cn1 cn0 (038/078/0b8/0f8) (138/178/1b8/1f8)
semiconductor group 177 sab 82538 saf 82538 async mode interrupt vector address (write) value after reset: 00 h note: unused bits have to be set to logical 0. iva is accessible via eight channel addresses (38 h to 1f8 h ). version 2 upward provides dynamic adjustment of channel priorities by programming the highest priority channel. selection of the highest priority channel is done with every write access to iva in conjunction with the channel assigned iva register address: iva register address: highest priority channel 38 h 0 78 h 1 b8 h 2 f8 h 3 138 h 4 178 h 5 1b8 h 6 1f8 h 7 the priority level becomes valid with the end of the write access to the iva register (rising edge of wr or ds, whichever applies) and remains stable until a new write access to this register occurs. t7C t6 device address these bits define the value of bits 6 and 7 of the interrupt vector which is sent out on the data bus (d0d7) during the interrupt acknowledge cycle. t5 device address version 1: device address this bit defines the value of bit 5 of the interrupt vector which is sent out on the data bus (d0d7) during the interrupt acknowledge cycle. version 2: device address extension in interrupt vector mode 2 (bit eda set) this bit defines the value of bit 5 of the interrupt vector which is sent out on the data bus (d0d7) during the interrupt acknowledge cycle. 70 iva t7 t6 t5 t4 t3 t2 rot eda (038/078/0b8/0f8) (138/178/1b8/1f8)
semiconductor group 178 sab 82538 saf 82538 async mode t4C t2 device address extension in interrupt vector mode 2 (bit eda set) these bits define the value of bits 2 to 4 of the interrupt vector which is sent out on the data bus (d0d7) during the interrupt acknowledge cycle. rot rotating interrupt priority (version 2 upward) version 1: this bit is unused and has to be set to logical 0. version 2: 0 fixed interrupt priority the relative order of the interrupt priority level assigned to the channels is fixed ( refer to chapter 2.3.1 ). 1 rotating interrupt priority the interrupt priority level will be adjusted after an interrupt has been serviced. together with bit ipc.rotm the interrupt priority mode is selected. ipc.rotm = 0: the priority level of all 8 serial channels are adjusted. ipc.rotm = 1: the priority level of only 7 channels are adjusted while one channel is fixed. eda extended device address if set, bits 2 to 5 (version 1: bits 2 to 4) of the generated interrupt vector contain the device address extension t2t5 (version 1: t2t4) instead of the channel number. for detailed information refer to chapter 2.2.3 . interrupt port configuration (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. ipc is accessible via eight channel addresses (039 h to 1f9 h ). vis masked interrupts visible (version 2 upward) 0 masked interrupt status bits are not visible. 1 masked interrupt status bits are visible. 70 ipc vis rotm sla2 sla1 sla0 casm ic1 ic0 (039/079/0b9/0f9) (139/179/1b9/1f9)
semiconductor group 179 sab 82538 saf 82538 async mode rotm rotating interrupt priority mode (version 2 upward) together with bit iva.rot the interrupt priority mode is selected. 0 with iva.rot = 1 the priorities of all 8 serial channels are rotated cyclically after an interrupt has been serviced. the channel last serviced is assigned the lowest priority of all ( refer to chapter 2.2.3.1 ). 1 with iva.rot = 0 the priority adjustment is performed only on 7 channels while one channel is fixed to highest priority level ( refer to chapter 2.2.3.1 ). sla2 sla0 slave address only used in slave cascading mode (refer to casm). casm cascading mode 0 slave cascading mode pins ie0, ie1 and ie2 are used as inputs. interrupt acknowledge is accepted if an interrupt signal has been generated and the values on pins ie0, ie1and ie2 correspond to the programmed values in sla0, sla1 and sla2 (slave address). 1daisy chaining mode pin ie0 as interrupt enable output and pin ie1 as interrupt enable input are used for building a daisy chain. pin ie2 is not used. interrupt acknowledge is accepted if an interrupt signal has been generated and interrupt enable input ie1 is active during a subsequent inta cycle(s). if pin int goes active, interrupt enable output ie0 is immediately set to low. ic1C ic0 interrupt port configuration these bits define the function of the interrupt output stage (pin int): ioc1 ioc0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high
semiconductor group 180 sab 82538 saf 82538 async mode interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. additionally, tcd and rpf are reset when the corresponding interrupt vector is output. note: if bit ipc.vis is set to 1, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. tcd termination character detected the termination character (tcr) has been received or the execution of the rfrd command issued before has been completed. a data block is now available in the rfifo. the actual block length can be determined by reading register rbcl first. time time out the time-out limit has been exceeded. if the respective mask bit is reset (i.e. time interrupt is enabled), the received data stream is monitored for exceeding the fixed time limit after the last character has been received (time limit = 4 cfl; character frame length cfl includes start bit, character length, parity bit and stop bits). perr parity error only valid if parity check/generation is enabled. if set, a character with parity error has been received. if enabled via rfdf, parity error information is stored in rfifo in the status byte pertaining to that character. ferr framing error this bit indicates that a character has been received with a framing error, i.e. the receiver has detected a 0 in a stop bit position. if enabled via rfdf, this information is stored in rfifo in the status byte pertaining to that character. 70 isr0 tcd time perr ferr plla cdsc rfo rpf (offset: 3a)
semiconductor group 181 sab 82538 saf 82538 async mode plla dpll asynchronous this bit is only valid when the receive clock is supplied by the dpll and fm0, fm1 or manchester data encoding is selected. it is set when the dpll has lost synchronization. reception is disabled (idle is inserted) until synchronization has been regained. additionally, transmission is also interrupted if the transmit clock is derived from the dpll. cdsc carrier detect status change indicates that a state transition has occurred on cd. the actual state of cd can be read from the vstr register. rfo receive fifo overflow this interrupt is generated if rfifo is full and a further character is received. this interrupt can be used for statistical purposes and indicates that the cpu does not respond quickly enough to an rpf or tcd interrupt. rpf receive pool full this bit is set if rfifo is filled with data (character and optional status information) up to the programmed threshold level. note: this interrupt is only generated in interrupt mode.
semiconductor group 182 sab 82538 saf 82538 async mode interrupt status register 1 (read) value after reset: 00 h all bits are reset when isr1 is read. additionally, xpr is reset when the corresponding interrupt vector is output. note: if bit ipc.vis is set 1, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. brk break this bit is set when a break signal - static low level for a time equal to (character length + parity + stop bit(s)) C is detected on r d. brkt break terminated this bit is set when a break signal on r d is terminated. alls all sent this bit is set when the xfifo is empty and the last character is completely sent out on t d. xoff xoff character detected this interrupt status indicates that the currently received character matches the value specified via register xoff. the function is independent of the programming of bit mode.flon. tin timer interrupt the internal timer has expired (see also description of timr register). csc clear to send status change indicates that a state transition has occurred on cts. the actual state of cts can be read from star register (cts bit). xon xon character detected this interrupt status indicates that the currently received character matches the value specified via register xon. the function is independent of the programming of bit mode.flon. xpr transmit pool ready a data block of up to 32 bytes can be written to xfifo. 70 isr1 brk brkt alls xoff tin csc xon xpr (offset: 3b)
semiconductor group 183 sab 82538 saf 82538 async mode interrupt mask register 0, 1 (write) value after reset: ff h , ff h each interrupt source can generate an interrupt signal at port int (characteristics of the output stage are defined via register ipc). a 1 in a bit position of imr0 or imr1 sets the mask active for the interrupt status in isr0 or isr1. masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit ipc.vis is set to 0 C be displayed in the interrupt status register if bit ipc.vis is set to 1. note: after reset, all interrupts are dis abled. 70 imr0 tcd time perr ferr plla cdsc rfo rpf (offset: 3a) imr1 brk brkt alls xoff tin csc xon xpr (offset: 3b)
semiconductor group 184 sab 82538 saf 82538 async mode port value register port a...d (read/write) note: unused bits have to be set to logical 0. each pvr register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin with the same number.(e.g. pvra.0 to port pin pa0) read access pvr shows the value of all pins (input and output). input values can be separated via software by and-ing pcr and pvr. write access pvr accepts values for all output pins (defined via pcr). values written to input pin locations are ignored. 70 pvra pvr7 pvr0 (03c/07c) pvrb pvr7 pvr0 (0bc/0fc) pvrc pvr7 pvr0 (13c/17c) pvrd 0 0 0 0 pvr3 pvr0 (1bc/1fc)
semiconductor group 185 sab 82538 saf 82538 async mode port interrupt status register port a...d (read) each pis register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin with the same number (e.g. pisa.0 to pin pa0). bit pisn is set and an interrupt is generated on int if C the corresponding universal port pin pn is defined as input via register pcr and C the interrupt source is enabled by resetting the corresponding interrupt mask pimn in register pim and C state transition has occurred on pin pn. for definite detection of a real state transition, pulse width should not be shorter than 20 ns. note: bits pisn are reset when register pis is read. masked interrupts are not normally indicated when pis is read. instead, they remain internally stored and pending. a pending interrupt is generated when the corresponding mask bit is reset to zero. however, if bit ipc.vis is set to 1, interrupt statuses in pis may be flagged although they are masked via register pim. these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. if more than one consecutive state transitions occurs on the same pin before the pis register is read, only one interrupt request will be generated. 70 pisa pis7 pis0 (03d/07d) pisb pis7 pis0 (0bd/0fd) pisc pvr7 pis0 (13d/17d) pisd 0 0 0 0 pis3 pis0 (1bd/1fd)
semiconductor group 186 sab 82538 saf 82538 async mode port interrupt mask register port a...d (write) value after reset: ff h note: unused bits have to be set to logical 0. each pim register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin and to the bits of register pis with the same number (e.g. pima.0 to pin pa0). 0interrupt source is enabled. 1interrupt source is disabled. a 1 in a bit position of pim sets the mask active for the interrupt status in pis. masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit ipc.vis is set to 0 C be displayed in the interrupt status register if bit ipc.vis is set to 1. refer to description of register pis. note: after reset, all interrupt sources are dis abled. 70 pima pim7 pim0 (03d/07d) pimb pim7 pim0 (0bd/0fd) pimc pim7 pim0 (13d/17d) pimd 0 0 0 0 pim3 pim0 (1bd/1fd)
semiconductor group 187 sab 82538 saf 82538 async mode port configuration register port a...d (read/write) value after reset: ff h note: unused bits have to be set to logical 0. each pcr register is accessible via two channel addresses. each of the above bits is assigned to the universal port pin (p0p7) with the same number(e.g. pcra.0 to pin pa0). if bit pcrn ( n = 07) is set to 0pin pn is defined as output. 1pin pn is defined as input. note: after reset, all pins of the universal port are defined as in puts. 70 pcra pcr7 pcr0 (03e/07e) pcrb pcr7 pcr0 (0be/0fe) pcrc pcr7 pcr0 (13e/17e) pcrd 0 0 0 0 pcr3 pcr0 (1be/1fe)
semiconductor group 188 sab 82538 saf 82538 bisync mode 4.3 status/control registers in bisync mode 4.3.1 register addresses table 11 register addresses in bisync mode *) all channel assigned addresses enable access to the same register(s) note: read access to unused register addresses: value should be ignored, write access to unused register addresses: should be avoided, or set to 00 h . address (a8 a0) register channel 0 1 2 3 4 5 6 7 read write 000 01f 040 05f 080 09f 0c0 0df 100 11f 140 15f 180 19f 1c0 1df rfifo xfifo 020 060 0a0 0e0 120 160 1a0 1e0 star cmdr 021 061 0a1 0e1 121 161 1a1 1e1 pre 022 062 0a2 0e2 122 162 1a2 1e2 mode 023 063 0a3 0e3 123 163 1a3 1e3 timr 024 064 0a4 0e4 124 164 1a4 1e4 synl 025 065 0a5 0e5 125 165 1a5 1e5 synh 026 066 0a6 0e6 126 166 1a6 1e6 tcr 027 067 0a7 0e7 127 167 1a7 1e7 dafo 028 068 0a8 0e8 128 168 1a8 1e8 rfc 029 069 0a9 0e9 129 169 1a9 1e9 02a 06a 0aa 0ea 12a 16a 1aa 1ea rbcl xbcl 02b 06b 0ab 0eb 12b 16b 1ab 1eb rbch xbch 02c 06c 0ac 0ec 12c 16c 1ac 1ec ccr0 02d 06d 0ad 0ed 12d 16d 1ad 1ed ccr1 02e 06e 0ae 0ee 12e 16e 1ae 1ee ccr2 02f 06f 0af 0ef 12f 16f 1af 1ef ccr3 030 070 0b0 0f0 130 170 1b0 1f0 tsax 031 071 0b1 0f1 131 171 1b1 1f1 tsar 032 072 0b2 0f2 132 172 1b2 1f2 xccr 033 073 0b3 0f3 133 173 1b3 1f3 rccr 034 074 0b4 0f4 134 174 1b4 1f4 vstr bgr 035 075 0b5 0f5 135 175 1b5 1f5 036 076 0b6 0f6 136 176 1b6 1f6 037 077 0b7 0f7 137 177 1b7 1f7 038, 078, 0b8, 0f8, 138, 178, 1b8, 1f8 gis *) iva *) 039, 079, 0b9, 0f9, 139, 179, 1b9, 1f9 ipc *) 03a 07a 0ba 0fa 13a 17a 1ba 1fa isr0 imr0 03b 07b 0bb 0fb 13b 17b 1bb 1fb isr1 imr1 03c, 07c 0bc, 0fc 13c, 17c 1bc, 1fc pvrad 03d, 07d 0bd, 0fd 13d, 17d 1bd, 1fd pisad pimad 03e, 07e 0be, 0fe 13e, 17e 1be, 1fe pcrad 03f, 07f 0bf, 0ff 13f, 17f 1bf, 1ff
semiconductor group 189 sab 82538 saf 82538 bisync mode 4.3.2 register definitions receive fifo (read) rfifo (offset: 001f) received data stored in rfifo (lsb is received first) can be organized in one of two selectable ways ( refer to figure 50 ): C pure data up to a character length of 8 bits (incl. optional parity) C additionally, one status byte per character with information about parity (if enabled) and parity error. reading data from rfifo can be done in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is received first from the serial interface. figure 50 organization of rfifo
semiconductor group 190 sab 82538 saf 82538 bisync mode interrupt controlled data transfer (interrupt mode) selected if dma bit in xbch is set to 0 up to 32 bytes/16 words of received data can be read from the rfifo following a rpf or a tcd interrupt depending on the selected rfifo mode (refer to rfc register): rpf interrupt: a fixed number of bytes/words (programmed threshold level rfth0, 1) has to be read by the cpu. tcd interrupt: termination character detected. the received data stream is monitored for termination character (programmable via register tcr). the number of valid bytes in rfifo is determined by reading the rbcl register. if necessary, the cpu can access the rfifo by issuing rfifo read command (cmdr.rfrd) before threshold level or the termination condition is reached. the number of valid bytes is determined by reading the rbcl register. additional information: star.rfne: rfifo not empty. dma controlled data transfer (dma mode) selected if dma bit in xbch is set. if the rfifo contains the number of bytes/words defined via the threshold level, the escc8 autonomously requests a dma block data transfer by dma by activating the drrn line until the last valid data is read (the ddrn line remains active up to the beginning of the last read cycle). this forces the dma controller to continuously perform bus cycles till all data is transferred from the escc8 to the system memory (level triggered transfer mode of dma controller). if the end condition (tcd) is reached, the same procedure as above is performed. drrn is activated until the termination character is transferred. a tcd interrupt is issued after the last data has been transferred. generation of further dma requests is blocked until tcd interrupts has been acknowledged by issuing an rmc command. the valid byte count of the last block can be determined by reading the rbcl register following the tcd interrupt. note: addresses within the 32-byte address space of the fifo all point to the same byte/word, i.e. current data can be accessed with any address within the valid scope. transmit fifo (write) xfifo (offset: 001f) writing data to xfifo can be in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. the lsb is transmitted first.
semiconductor group 191 sab 82538 saf 82538 bisync mode interrupt mode selected if dma bit in xbch is reset. up to 32 bytes/16 words of transmit data can be written to the xfifo following an xpr interrupt. dma mode selected if dma bit in xbch is set. prior to any data transfer, the actual byte count to be transmitted must be written to the xbch, xbcl registers by the user. correct transmission of data in the case of word access and of an odd number of bytes specified in xbch, xbcl is guaranteed. if data transfer is then initiated via the cmdr register (command xf), the escc8 autonomously requests the correct amount of block data transfers (n bw + rest; bw = 32, 16; n = 0, 1,). note: addresses within the 32-byte address space of the fifo all point to the same byte/word, i.e. current data can be accessed with any address within the valid range. status register (read) xdov transmit data overflow more than 32 bytes have been written to the xfifo. this bit is reset by: C a transmitter reset command xres C or when all bytes in the accessible half of the xfifo have been moved into the inacessible half. xfw transmit fifo write enable data can be written to the xfifo. rfne rfifo not empty this bit is set if the accessible part of rfifo holds at least one valid byte. sync... synchronization status the bit is reset after the hunt command has been issued. it indicates that the receiver has lost synchronization and is searching for the presence of a syn character. if found, sync will be immediately set, the scd interrupt is generated (if enabled), and filling the rfifo with received data is started. 70 star xdov xfw rfne sync 0 cec cts 0 (offset: 20)
semiconductor group 192 sab 82538 saf 82538 bisync mode cec command executing 0 no command is currently executed, the cmdr register can be written to. 1 a command (written previously to cmdr) is currently executed, no further command can be temporarily written in cmdr register. note: cec will be active at most 2.5 transmit clock periods. if the escc8 is in power down mode cec will stay active. cts clear to send state this bit indicates the state of the cts pin. 0 cts is inactive (high) 1 cts is active (low) command register (write) value after reset: 00 h note: the maximum time between writing to the cmdr register and the execution of the command is 2.5 clock cycles. therefore, if the cpu operates with a very high clock rate in comparison with the escc8s clock, it is recommended that the cec bit of the star register be checked before writing to the cmdr register to avoid any loss of commands. rmc receive message complete confirmation from cpu to escc8 that the current data block has been fetched following a rpf or tcd interrupt or following a user initiated read access in conjunction with the rfifo read command rfrd; the occupied space in the rfifo can be released. note: in dma mode, this command has to be issued after a tcd interrupt in order to enable the generation of further receiver dma requests. rres receiver reset all data in rfifo and bisync receiver is deleted. 70 cmdr rmc rres rfrd sti xf hunt xme xres (offset: 20)
semiconductor group 193 sab 82538 saf 82538 bisync mode rfrd receive fifo read enable the cpu can have access to rfifo by issuing the rfrd command before threshold level or the end condition (tcd) are fulfilled. after issuing the rfrd command, the cpu has to wait for tcd interrupt, before reading rbc and rfifo. the number of valid bytes is determined by reading the rbcl register. sti start timer the internal timer is started. note: the timer is stopped by rewriting the timr register after start. xf transmit frame l interrupt mode after having written up to 32 bytes/16 words to the xfifo, this command initiates the transmission of data. l dma mode after having written the amount of data to be transmitted to the xbch, xbcl registers, this command initiates the data transfer from system memory to escc8 by dma. serial data transmission starts as soon as 32 bytes/16 words are stored in the xfifo or the transmit byte counter value is reached. hunt... enter hunt phase this command forces the receiver to immediately go into the hunt state. synchronization is lost and the receiver starts searching for syn characters. xme... transmit message end (used in interrupt mode only!) indicates that the data block written last to the transmit fifo completes the current frame. the escc8 can terminate the transmission operation properly by appending the crc sequence to the data. after that, idle is transmitted. in dma mode, the end of the frame is determined by the transmit byte count in xbch, xbcl, thus, xme is not used in this case. xres transmitter reset xfifo is cleared of any data and idle (logical 1s) is transmitted. this command can be used by the cpu to abort current data transmission. in response to xres an xpr interrupt is generated.
semiconductor group 194 sab 82538 saf 82538 bisync mode preamble register (write) value after reset: 00 h this register defines the 8-bit pattern which is sent out during preamble transmission (refer to register ccr3). mode register (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. slen... syn character length this bit selects the length of the syn character: 0...6 bit (monosync) / 12 bit (bisync) 1...8 bit (monosync) / 16 bit (bisync) bisnc... enable bisync mode 0...monosync mode is enabled (6/8 bit syn character defined via register synl). 1...bisync mode is enabled (12/16 bit syn character defined via registers synl and synh). synl is received/transmitted first. rac receiver active switches the receiver to operational or inoperational state. 0 receiver inactive 1 receiver active rts request to send defines the state and control of rts pin. 0 the rts pin is controlled by the escc8 autonomously. rts is activated when data transmission starts and deactivated when transmission is completed. 1 the rts pin is controlled by the cpu. if this bit is set, the rts pin is activated immediately and remains active till this bit is reset. 70 pre pr7 pr0 (offset: 21) 70 mode 0 0 slen bisnc rac rts trs tlp (offset: 22)
semiconductor group 195 sab 82538 saf 82538 bisync mode trs timer resolution selects the resolution of the internal timer (factor k , see description of timr register): 0 k = 32 768 1 k = 512 tlp test loop input and output of the bisync channels are internally connected. (e.g. transmitter channel 0 - receiver channel 0) timer register (read/write) value (5 bits) sets the time period t1 as follows: t 1 = k (value + 1) tcp where C k is the timer resolution factor which is either 32 768 or 512 clock cycles dependent on the programming of trs bit in mode. C tcp is the clock period of transmit data. cnt (3 bits) cnt plus value determine the time period t 2 after which a timer interrupt will be generated. the time period t 2 is t 2 = 32 k cnt tcp + t 1 . if cnt is set to 7, a timer interrupt is periodically generated after the expiration of t 1 . 70 timr cnt value (offset: 23)
semiconductor group 196 sab 82538 saf 82538 bisync mode syn character register low, high (read/write) value after reset: 00, 00 h in conjunction with bit bisnc and bit slen the syn character can be specified: C monosync mode (bisnc = 0) the syn character is defined by synl. slen = 0: the syn character is specified by bits 0-5 slen = 1: the syn character is specified by bits 0-7 C bisync mode (bisnc = 1) the syn character is defined by synl (low byte) and synh (high byte). slen = 0: the 12-bit syn character is specified by bits 0-5 of both synl and synh slen = 1: the 16-bit syn character is specified by bits 0-7 of both synl and synh synl is received/transmitted first in transmit direction, the syn character thus specified is sent continuously when no data are to be transmitted and itf (interframe time fill) control bit is set to 1. in receive direction, the receiver searches for the specified syn character in the receive data stream, when in hunt mode. termination character register (read/write) value after reset: 00 h tcr7Ctcr0 termination character if enabled via register rfc the received data stream is monitored for the occurrence of a programmed termination character. when such a character is found, an interrupt is issued if enabled via mask register imr0. the number of valid bytes in the rfifo up to and including the termination character is determined by reading the rbcl register. note: if selected character length is less than eight bits, leading (unused) bits of tcr have to be set to 0. 70 synl synl (offset: 24) synh synh (offset: 25) 70 tcr tcr7 tcr0 (offset: 26)
semiconductor group 197 sab 82538 saf 82538 bisync mode data format (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. par1, par0 parity format if parity check/generation is enabled by setting pare, these bits define the parity type: 00 space (0) 01 odd parity 10 even parity 11 mark (1) the received parity bit is stored in rfifo C as leading bit immediately preceding the character if character length is 5 to 7 bits and rfc.dps is set to 0, and as lsb of the status byte pertaining to the character if the corresponding rfifo data format is enabled. C as lsb of the status byte pertaining to the character if character length is 8 bits and the corresponding rfifo data format is enabled. parity error is indicated in the msb of the status byte pertaining to the character, if enabled. additionally, a parity error interrupt can be generated. pare parity enable 0 parity check/generation disabled 1 parity check/generation enabled chl1Cchl0 character length these bits define the length of received and transmitted characters, excluding optional parity: 00 8 bit 01 7 bit 10 6 bit 11 5 bit 70 dafo 0 0 0 par1 par0 pare chl1 chl0 (offset: 27)
semiconductor group 198 sab 82538 saf 82538 bisync mode rfifo control register (read/write) value after reset: 00h note: unused bits have to be set to logical 0. dps disable parity storage only valid if parity check/generation is enabled via dafo.pare and character length is less than 8 bits. 0 the parity bit is stored 1 the parity bit is not stored in the data byte of rfifo. note: the parity bit is always stored in the status byte. sload... enable syn character load 0...all data except syn characters are stored in rfifo. 1...storage of all received syn characters to rfifo is enabled. 70 rfc 0 dps sload rfdf rfth1 rfth0 0 tcde (offset: 28)
semiconductor group 199 sab 82538 saf 82538 bisync mode rfdf rfifo data format 0 only data bytes (character plus optional parity up to 8 bit) are stored. 1 additionally to every data byte, an attached status byte is stored. pe : parity error p : parity bit (p): can be disabled via bit dps rfth1, rfth0 rfifo threshold level these bits define the level up to which rfifo is filled with valid data: d: data byte s: status byte if the threshold level is reached, the rpf interrupt is generated if enabled. after rpf is generated, the contents of rfifo (rfth bytes) can be read rfdf = 0 rfdf = 1 C character 5 C 8 bit or C character 5 C 7(8)* bit + parity * : parity bit is lost C character 5 C 8 bit + status or C character 5 C 7(8)* bit + parity + status * : parity bit is in status byte rfth1, 0 threshold level (bytes) rfdf = 0 rfdf = 1 00 01 10 11 1 ( 1d) 4 ( 4d) 16 (16d) 32 (32d) 2 ( 1d + 1s) 4 ( 2d + 2s) 16 ( 8d + 8s) 32 (16d + 16s) 74 0 data byte (p) char 74 0 data byte (p) char 70 status byte pe p
semiconductor group 200 sab 82538 saf 82538 bisync mode by the cpu. to indicate that this rfifo pool can be released, an rmc command has to be issued. tcde termination character detection enable when this bit is set, the received data stream is monitored for termination character (tcr register). when such a character occurs, the tcd interrupt is generated if enabled via mask register imr0. the number of bytes to be read from rfifo is determined by the value of rbcl. receive byte count low (read) indicates the number of valid bytes available in the accessible part of the rfifo. this register must be read by the cpu following a tcd interrupt. in case of a tcd interrupt the number of valid bytes in the accessible part of the rfifo can be evaluated by and-ing the contents of rbcl with: threshold level (bytes) C 1. rbc is reset with rmc after preceeding tcd interrupt. in case of rpf interrupt rbc is incremented by threshold level (bytes). transmit byte count low (write) together with xbch (bits xbc11xbc8) this register is used in dma mode only, to program the length (14096 bytes) of the next data block to be transmitted. in terms of the value xbc, programmed in xbc11xbc0 (xbc = 04095), the length of the block in number of bytes is: length = xbc + 1. this allows the escc8 to request the correct amount of dma cycles after an xf command in cmdr. 70 rbcl rbc7 rbc0 (offset: 2a) threshold level mask 4 16 32 03 h 0f h 1f h 70 xbcl xbc7 xbc0 (offset: 2a)
semiconductor group 201 sab 82538 saf 82538 bisync mode received byte count high (read) value after reset: 000xxxxx dma, cas these bits represent the read-back value programmed in xbch rbc11C rbc8 receive byte count (most significant bits) no function. transmit byte count high (write) value after reset: 000xxxxx note: unused bits have to be set to logical 0. dma dma mode selects the data transfer mode of escc8 to/from system memory. 0 interrupt controlled data transfer (interrupt mode). 1 dma controlled data transfer (dma mode). cas carrier detect auto start when set, a high on the cd pin enables the corresponding receiver and data reception is started. when not set, if not in clock mode 1 or 5, the cd pin can be used as a general input. xc transmit continuously only valid if dma mode is selected. if the xc bit is set, the escc8 continuously requests for transmit data ignoring the transmit byte count programmed via xbch, xbcl. xbc11C xbc8 transmit byte count (most significant bits) valid only if dma mode is selected. together with xbcl (bits xbc7xbc0), determine the number of characters to be transmitted. 70 rbch dma 0 cas 0 rbc11 rbc8 (offset: 2b) see xbch 70 xbch dma 0 cas xc xbc11 xbc8 (offset: 2b)
semiconductor group 202 sab 82538 saf 82538 bisync mode channel configuration register 0 (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. pu switches between power up and power down mode 0 power down (standby) 1 power up (active) mce master clock enable if this bit is set to 1, the clock provided via pin xtal1 works as master clock to allow full functionality of the microprocessor interface (access to all status and control registers, dma and interrupt support) independent of the receive and the transmit clocks. the internal oscillator in conjunction with a crystal on xtal1-2 can be used, too. the master clock option is not applicable in clock mode 5. refer to table 5 for more details. note: the internal timers run with the master clock. sc2C sc0 serial port configuration 000 nrz data encoding 001 (not recommended) 010 nrzi data encoding 011 (not recommended) 100 fm0 data encoding 101 fm1 data encoding 110 manchester data encoding 111 (not used) sm1C sm0 serial mode 00 hdlc/sdlc mode 01 sdlc loop mode 10 bisync mode 11 async mode 70 ccr0 pu mce 0 sc2 sc1 sc0 sm1 sm0 (offset: 2c)
semiconductor group 203 sab 82538 saf 82538 bisync mode channel configuration register 1 (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. ods output driver select defines the function of the transmit data pins (t da, t db) 0 t d pin is an open drain output. 1 t d pin is a push-pull output. itf... interframe time fill format determines the idle (= no data to send) state of the transmit data pin (t d) 0...continuous logical 1 is output. 1...continuous syn characters are output. cm2C cm0 clock mode selects one of 8 different clock modes: 000 clock mode 0 ?? ?? ?? 111 clock mode 7 note: clock mode 5 is only specified for version sab 82538h-10, not for sab 82538h. 70 ccr1 0 0 0 ods itf cm2 cm0 (offset: 2d)
semiconductor group 204 sab 82538 saf 82538 bisync mode channel configuration register 2 (read/write) value after reset: 00 h the meaning of the individual bits in ccr2 depends on the clock mode selected via ccr1 as follows: note: unused bits have to be set to logical 0. soc1, soc0 special output control in a bus configuration (selected via ccr0) defines the function of pin rts as follows: 0x rts output is activated during transmission of characters. 10 rts output is always high ( rts disabled). 11 rts indicates the reception of a data frame (active low). in a point-to-point configuration (selected via ccr0) the t d and r d pins may be flipped 0x data is transmitted on t d, received on r d (normal case). 1x data is transmitted on r d, received on t d. br9, br8 baud rate, bit 9-8 high order bits, see description of bgr register. xcs0, rcs0... transmit/receive clock shift, bit 0 together with xcs2, xcs1 (rcs2, rcs1) in tsax (tsar), determines the clock shift relative to the frame synchronization signal of the transmit (receive) time-slot. a clock shift of 0 ... 7 bits is programmable (clock mode 5 only). 70 ccr2 clock mode 0a, 1 soc1 soc0 0 0 0 rwx 0 div (offset: 2e) clock mode 0b, 2, 3, 6, 7 br9 br8 bdf ssel toe rwx 0 div clock mode 4 soc1 soc0 0 0 toe rwx 0 div clock mode 5 soc1 soc0 xcs0 rcs0 toe rwx 0 div
semiconductor group 205 sab 82538 saf 82538 bisync mode bdf... baud rate division factor 0the division factor of the baud rate generator is set to 1 (constant). 1the division factor is determined by br9 - br0 bits in ccr2 and brg registers. ssel... clock source select selects the clock source in clock modes 0, 2, 3, 6 and 7 ( refer to table 5 ). toe... t clk output enable 0 t clk pin is input 1 t clk pin is switched to output function if applicable to the selected clock mode ( refer to table 5 ). rwx... read/write exchange valid only in dma mode. if this bit is set, the C rd and wr pins are internally exchanged (siemens/intel bus interface) C r/ w pin is inverted in polarity (motorola bus interface) while any dack input is active. this useful feature allows a simple interfacing to the dma controller. note: the rwx bit of all eight channels is ored. div... data inversion only valid if nrz data encoding is selected. data is transmitted and received inverted. channel configuration register 3 (read/write) (version 2 upwards) value after reset: 00 h pre1...pre0... number of preamble repetition if preamble transmission is enabled, the preamble defined via register pre is transmitted 00...1 times 01...2 times 10...4 times 11...8 times. 70 ccr3 pre1 pre0 ept con crl capp crcm psd (offset: 2f)
semiconductor group 206 sab 82538 saf 82538 bisync mode ept... enable preamble transmission this bit enables transmission of a preamble. the preamble is started after interframe time fill transmission has been stopped and a new block of data is about to be transmitted. the preamble consists of an 8-bit pattern defined via register pre which is repeated a number of times selected by bits pre0 and pre1. con... crc on this bit determines whether the current data written to xfifo has to be included into crc calculation or not. it has to be programmed before the assigned byte/word is written to xfifo. in the case of word access, both characters are included. since this control bit is copied in the xfifo every time a character is written, it is not necessary to reprogram it for each character when consecutive characters are to be either all included into or all excluded from crc calculation. 0...data not included 1...data included. crl... crc reset level this bit defines the initialization for internal transmit crc generator. 0...initialized to ffff h . 1...initialized to 0000 h . note: the internal transmit crc generator is automatically initialized before transmission of a new frame starts. capp... crc append if this bit is set, the internal transmit crc generator is activated: 1. the crc generator is initialized every time the transmission of a new frame starts. initialization value is defined via bit crl. 2. during transmission all data with the con bit set to 1 are included into crc checksum calculation. 3. the checksum is automatically appended to the last transmitted data of the frame if a transmit message end command (xme) has been issued. crcm... select crc algorithm selects the crc algorithm for the internal transmit crc generator: 0...crc-16 (x 16 + x 15 + x 2 + 1) 1...crc-ccitt (x 16 + x 12 + x 5 + 1) psd... dpll phase shift disable only applicable in the case of nrz and nrzi encoding. if this bit is set to 1, the phase shift function of the dpll is disabled. in this case the windows for phase adjustment are extended.
semiconductor group 207 sab 82538 saf 82538 bisync mode time-slot assignment register transmit (write) this register is only used in clock mode 5! value after reset: 00 h tsnx time-slot number transmit selects one of up 64 possible time-slots (00 h -3f h ) in which data is transmitted. the number of bits per time-slot can be programmed via xccr. xcs2 xcs1 transmit clock shift, bit 2-1 together with bit xcs0 in ccr2, transmit clock shift can be adjusted. time-slot assignment register receive (write) this register is only used in clock mode 5! value after reset: 00 h tsnr time-slot number receive defines one of up to 64 possible time-slots (00 h -3f h ) in which data is received. the number of bits per time-slot can be programmed via rccr. rcs2C rcs1 receive clock shift, bit 2-1 together with bit rcs0 in ccr2, the receive clock shift can be adjusted. 70 tsax tsnx xcs2 xcs1 (offset: 30) 70 tsar tsnr rcs2 rcs1 (offset: 31)
semiconductor group 208 sab 82538 saf 82538 bisync mode transmit channel capacity register (write) this register is only used in clock mode 5! value after reset: 00 h xbc7C xbc0 transmit bit number count, bit 7-0 defines the number of bits to be transmitted within a time-slot: number of bits = xbc + 1 (1 256 bits/time-slot). receive channel capacity register (write) this register is only used in clock mode 5! value after reset: 00 h rbc7C rbc0 receive bit count, bit 7-0 defines the number of bits to be received within a time-slot: number of bits = rbc + 1 (1256 bits/time-slot). version status register (read) cd carrier detect this bit reflects the state of the cd pin. 1 cd active 0 cd inactive dpla dpll asynchronous this bit is only valid when the receive clock is supplied by the dpll and fm0, fm1 or manchester data encoding is selected. it is set when the dpll has lost synchronization. reception is disabled (idle is inserted) until synchronization has been regained. additionally, transmission is interrupted, too, if the transmit clock is derived from the dpll (same effect as the deactivation of pin cts). 70 xccr xbc7 xbc0 (offset: 32) 70 rccr rbc7 rbc0 (offset: 33) 70 vstr cd dpla 0 0 vn3 vn0 (offset: 34)
semiconductor group 209 sab 82538 saf 82538 bisync mode vn3C vn0 version number of chip 0version 1 1 version 2 baud rate generator register (write) br7C br0 baud rate, bits 7-0 together with bits br9, br8 of ccr2, it determines the division factor of the baud rate generator. in terms of the value n programmed in br9 - br0 ( n = 01023), the division factor k is: k = ( n + 1) 2 global interrupt status register (read) value after reset: 00 h this status register points to pending C channel assigned interrupts (isr0_x, isr1_x) C universal port interrupts (pisad). gis is accessible via eight channel addresses (038 h to 1f8 h ). piaC pid port interrupt indication these status bits point to pending interrupts in corresponding port interrupt status registers pisapisd. they may be set independently from channel assigned interrupts. cii channel interrupt indication set if at least one interrupt source of any channel is active. 70 bgr br7 br0 (offset: 34) 70 gis pia pib pic pid cii cn2 cn1 cn0 (038/078/0b8/0f8) (138/178/1b8/1f8)
semiconductor group 210 sab 82538 saf 82538 bisync mode cn2C cn0 channel number (07) if at least one interrupt source is active (bit cii is set), these bits point to the channel with currently highest source priority. refer to chapter 2.2.3 for detailed description of the priority structure. contents of register gis are frozen after every input acknowledge cycle. C after the first read access to gis after the interrupt vector has been output, C after every read access to anyone of the channel assigned interrupt status registers, C during every inta cycle. interrupt vector address (write) value after reset: 00 h note: unused bits have to be set to logical 0. iva is accessible via eight channel addresses (38 h to 1f8 h ). version 2 upward provides dynamic adjustment of channel priorities by programming the highest priority channel. selection of the highest priority channel is done with every write access to iva in conjunction with the channel assigned iva register address: iva register address: highest priority channel 38 h 0 78 h 1 b8 h 2 f8 h 3 138 h 4 178 h 5 1b8 h 6 1f8 h 7 the priority level becomes valid with the end of the write access to the iva register (rising edge of wr or ds, whichever applies) and remains stable until a new write access to this register occurs. t7C t6 device address these bits define the value of bits 6 and 7 of the interrupt vector which is sent out on the data bus (d0d7) during the interrupt acknowledge cycle. 70 iva t7 t6 t5 t4 t3 t2 rot eda (038/078/0b8/0f8) (138/178/1b8/1f8)
semiconductor group 211 sab 82538 saf 82538 bisync mode t5 device address version 1: device address this bit defines the value of bit 5 of the interrupt vector which is sent out on the data bus (d0d7) during the interrupt acknowledge cycle. version 2: device address extension in interrupt vector mode 2 (bit eda set) this bit defines the value of bit 5 of the interrupt vector which is sent out on the data bus (d0d7) during the interrupt acknowledge cycle. t4C t2 device address extension in interrupt vector mode 2 (bit eda set) these bits define the value of bits 2 to 4 of the interrupt vector which is sent out on the data bus (d0d7) during the interrupt acknowledge cycle. rot rotating interrupt priority (version 2 upward) version 1: this bit is unused and has to be set to logical 0. version 2: 0 fixed interrupt priority the relative order of the interrupt priority level assigned to the channels is fixed ( refer to chapter 2.3.1 ). 1 rotating interrupt priority the interrupt priority level will be adjusted after an interrupt has been serviced. together with bit ipc.rotm the interrupt priority mode is selected. ipc.rotm = 0: the priority level of all 8 serial channels are adjusted. ipc.rotm = 1: the priority level of only 7 channels are adjusted while one channel is fixed. eda extended device address if set, bits 2 to 5 (version 1: bits 2 to 4) of the generated interrupt vector contain the device address extension t2t5 (version 1: t2t4) instead of the channel number. for detailed information refer to chapter 2.2.3 .
semiconductor group 212 sab 82538 saf 82538 bisync mode interrupt port configuration (read/write) value after reset: 00 h note: unused bits have to be set to logical 0. ipc is accessible via eight channel addresses (039 h to 1f9 h ). vis masked interrupts visible (version 2 upward) 0 masked interrupt status bits are not visible. 1 masked interrupt status bits are visible. rotm rotating interrupt priority mode (version 2 upward) together with bit iva.rot the interrupt priority mode is selected. 0 with iva.rot = 1 the priorities of all 8 serial channels are rotated cyclically after an interrupt has been serviced. the channel last serviced is assigned the lowest priority of all ( refer to chapter 2.2.3.1 ). 1 with iva.rot = 0 the priority adjustment is performed only on 7 channels while one channel is fixed to highest priority level ( refer to chapter 2.2.3.1 ). sla2 sla0 slave address only used in slave cascading mode (refer to casm). casm cascading mode 0 slave cascading mode pins ie0, ie1 and ie2 are used as inputs. interrupt acknowledge is accepted if an interrupt signal has been generated and the values on pins ie0, ie1and ie2 correspond to the programmed values in sla0, sla1 and sla2 (slave address). 1daisy chaining mode pin ie0 as interrupt enable output and pin ie1 as interrupt enable input are used for building a daisy chain. pin ie2 is not used. interrupt acknowledge is accepted if an interrupt signal has been generated and interrupt enable input ie1 is active during a subsequent inta cycle(s). if pin int goes active, interrupt enable output ie0 is immediately set to low. 70 ipc vis rotm sla2 sla1 sla0 casm ic1 ic0 (039/079/0b9/0f9) (139/179/1b9/1f9)
semiconductor group 213 sab 82538 saf 82538 bisync mode ic1C ic0 interrupt port configuration these bits define the function of the interrupt output stage (pin int): interrupt status register 0 (read) value after reset: 00 h all bits are reset when isr0 is read. additionally, tcd and rpf are reset when the corresponding interrupt vector is output. note: if bit ipc.vis is set to 1, interrupt statuses in isr0 may be flagged although they are masked via register imr0. however, these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. tcd termination character detected the termination character (tcr) has been received or the execution of the rfrd command issued before has been completed. a data block is now available in the rfifo. the actual block length can be determined by reading register rbcl first. perr parity error only valid if parity check/generation is enabled. if set, a character with parity error has been received. if enabled via rfdf, parity error information is stored in rfifo in the status byte pertaining to that character. scd... syn character detected only valid in hunt mode. this bit is set if a syn character is found in the received data stream after the hunt command has been issued. the receiver now is in the synchronous state. ioc1 ioc0 function x 0 1 0 1 1 open drain output push/pull output, active low push/pull output, active high 70 isr0 tcd 0 perr scd plla cdsc rfo rpf (offset: 3a)
semiconductor group 214 sab 82538 saf 82538 bisync mode plla dpll asynchronous this bit is only valid when the receive clock is supplied by the dpll and fm0, fm1 or manchester data encoding is selected. it is set when the dpll has lost synchronization. reception is disabled (idle is inserted) until synchronization has been regained. additionally, transmission is also interrupted if the transmit clock is derived from the dpll. cdsc carrier detect status change indicates that a state transition has occurred on cd. the actual state of cd can be read from the vstr register. rfo receive fifo overflow this interrupt is generated if rfifo is full and a further character is received. this interrupt can be used for statistical purposes and indicates that the cpu does not respond quickly enough to an rpf or tcd interrupt. rpf receive pool full this bit is set if rfifo is filled with data (character and optional status information) up to the programmed threshold level. note: this interrupt is only generated in interrupt mode. interrupt status register 1 (read) value after reset: 00 h all bits are reset when isr1 is read. additionally, xpr is reset when the corresponding interrupt vector is output. note: if bit ipc.vis is set to 1, interrupt statuses in isr1 may be flagged although they are masked via register imr1. however, these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. alls... all sent this bit is set when the xfifo is empty and the last character is completely sent out on t d. 70 isr1 0 0 alls xdu tin csc xmr xpr (offset: 3b)
semiconductor group 215 sab 82538 saf 82538 bisync mode xdu... transmit data underrun a block of data in transmission has been terminated with idle, because the xfifo contains no further data. note: transmitter and xfifo are reset and deactivated if this condition occurs. they are re-activated not before this interrupt status register has been read. thus, xdu should not be masked via register imr1. tin... timer interrupt the internal timer has expired (see also description of timr register). csc... clear to send status change indicates that a state transition has occurred on cts. the actual state of cts can be read from star register (cts bit). xmr... transmit message repeat the transmission of the last block of characters has to be repeated because - a collision has occurred when transmitting a character in a bus configuration, or - cts (transmission enable) has been withdrawn during transmission of a character in point-to-point configuration. xpr... transmit pool ready a data block of up to 32 bytes can be written to xfifo. interrupt mask register 0, 1 (write) value after reset: ff h , ff h note: unused bits have to be set to logical 1. each interrupt source can generate an interrupt signal at port int (function of the output stage is defined via register ipc). a 1 in a bit position of imr0 or imr1 sets the mask active for the interrupt status in isr0 or isr1. masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit ipc.vis is set to 0 C be displayed in the interrupt status register if bit ipc.vis is set to 1 note: after reset, all interrupts are dis abled. 70 imr0 tcd 1 perr scd plla cdsc rfo rpf (offset: 3a) imr1 1 1 alls xdu tin csc xmr xpr (offset: 3b)
semiconductor group 216 sab 82538 saf 82538 bisync mode port value register port a...d (read/write) note: unused bits have to be set to logical 0. each pvr register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin with the same number (e.g. pvra.0 to pin pa0). read access pvr shows the value of all pins (input and output). input values can be separated via software by and-ing pcr and pvr. write access pvr accepts values for all output pins (defined via pcr). values written to input pin locations are ignored. 70 pvra pvr7 pvr0 (03c/07c) pvrb pvr7 pvr0 (0bc/0fc) pvrc pvr7 pvr0 (13c/17c) pvrd 0 0 0 0 pvr3 pvr0 (1bc/1fc)
semiconductor group 217 sab 82538 saf 82538 bisync mode port interrupt status register port a...d (read) each pis register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin with the same number (e.g. pisa.0 to pin pa0). bit pisn is set and an interrupt is generated on int if C the corresponding universal port pin pn is defined as input via register pcr and C the interrupt source is enabled by resetting the corresponding interrupt mask pimn in register pim and C a state transition has occurred on pin pn. for definite detection of a real state transition, pulse width should not be shorter than 20 ns. note: bits pisn are reset when register pis is read. masked interrupts are not normally indicated when pis is read. instead, they remain internally stored and pending. a pending interrupt is generated when the corresponding mask bit is reset to zero. however, if bit ipc.vis is set to 1, interrupt statuses in pis may be flagged although they are masked via register pim. these masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are visible in register gis. if more than one consecutive state transitions occur on the same pin before the pis register is read, only one interrupt request will be generated. 70 pisa pis7 pis0 (03d/07d) pisb pis7 pis0 (0bd/0fd) pisc pis7 pis0 (13d/17d) pisd 0 0 0 0 pis3 pis0 (1bd/1fd)
semiconductor group 218 sab 82538 saf 82538 bisync mode port interrupt mask register port a...d (write) value after reset: ff h note: unused bits have to be set to logical 0. each pim register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin and to the bits of register pis with the same number (e.g. pima.0 to pin pa0). 0...interrupt source is enabled. 1...interrupt source is disabled. a 1 in a bit position of pim sets the mask active for the interrupt status in pis. masked interrupt statuses neither generate an interrupt vector or a signal on int, nor are they visible in register gis. moreover, they will C not be displayed in the interrupt status register if bit ipc.vis is set to 0 C be displayed in the interrupt status register if bit ipc.vis is set to 1. refer to description of register pis. note: after reset, all interrupt sources are disabled. 70 pima pim7 pim0 (03d/07d) pimb pim7 pim0 (0bd/0fd) pimc pim7 pim0 (13d/17d) pimd 0 0 0 0 pim3 pim0 (1bd/1fd)
semiconductor group 219 sab 82538 saf 82538 bisync mode port configuration register port a...d (read/write) value after reset: ff h note: unused bits have to be set to logical 0. each pcr register is accessible via two channel addresses. each of the above bits is assigned to the corresponding universal port pin with the same number (e.g. pcra.0 to pin pa0). if bit pcrn (n = 0...7) is set to 0...pin pn is defined as output. 1...pin pn is defined as input. note: after reset, all pins of the universal port are defined as inputs. 70 pcra pcr7 pcr0 (03e/07e) pcrb pcr7 pcr0 (0be/0fe) pcrc pcr7 pcr0 (13e/17e) pcrd 0 0 0 0 pcr3 pcr0 (1be/1fe)
sab 82538 saf 82538 semiconductor group 220 5 electrical specification 5.1 absolute maximum ratings supply voltage v dd = C 0.3 to + 7.0 v input voltage v i = C 0.3 to v dd + 0.3 v (max. 7 v) output voltage v 0 = C 0.3 to v dd + 0.3 v (max. 7 v) storage temperature t stg = C 65 to + 150 ?c note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. this is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. 5.2 dc characteristics sab t a = 0 to 70 ?c ; v dd = 5 v 5 %, v ss = 0 v saf t a = C 40 to 85 ?c ; v dd = 5 v 5 %, v ss = 0 v parameter symbol limit values unit test condition min. max. input low voltage (not xtal1, width) v il C 0.4 0.8 v input high voltage (not xtal1, width) v ih 2.0 v dd + 0.4 v input low voltage (width) v wil C 0.4 1.0 v input high voltage (width) v wih 3.5 v dd + 0.4 v input low voltage (xtal1) v xil C 0.4 0.5 v input high voltage (xtal1) v xih 3.5 v dd + 0.4 v
sab 82538 saf 82538 semiconductor group 221 dc characteristics (contd) 5.3 capacitances t a = 25 ?c ; v dd = 5 v 5 %, v ss = 0 v note 1: not tested in production. parameter symbol limit values unit test condition min. max. output low voltage v ol 0.45 v i ol =7ma (pins txd, rxd) i ol = 2 ma (all others except xtal2) output high voltage output high voltage v oh v oh 2.4 v dd C 0.5 v v i oh = C 400 m a i oh = C 100 m a power supply current operational i cc 40 ma v dd =5v c p = 2 mhz inputs at 0 v / v dd no output loads power down 6 ma input leakage current output leakage curr. i li i lo 10 m a 0v < v in < v dd to 0 v 0 v < v out < v dd to 0 v parameter symbol limit values unit typ. max. input capacitancenote 1 c in 510pf output capacitancenote 1 c out 815pf i/o capacitancenote 1 c io 10 20 pf
sab 82538 saf 82538 semiconductor group 222 5.4 ac characteristics sab t a = 0 to 70 ?c ; v dd = 5 v 5 %, v ss = 0 v saf t a = C 40 to 85 ?c ; v dd = 5 v 5 %, v ss = 0 v all inputs except xtal1 and width are driven to v ih = 2.4 v for a logical 1 and to v il = 0.4 v for a logical 0 xtal1 and width (cmos inputs) are driven to v ih = 4.0 v for a logical 1 and to v il = 0.4 v for a logical 0 timing measurements (except for xtal2) are made at v h = 2.0 v for a logical 1 and at v l = 0.8 v for a logical 0 timing measurements for xtal2 are made at v h = 3.5 v for a logical 1 and at v l = 1.0 v for a logical 0 the ac testing input/output waveforms are shown below. figure 51 input/output waveform for ac tests
sab 82538 saf 82538 semiconductor group 223 5.4.1 microprocessor interface 5.4.1.1 siemens/intel bus interface mode figure 52 siemens/intel non-multiplexed address timing figure 53 siemens/intel wr to rd control interval
sab 82538 saf 82538 semiconductor group 224 figure 54 siemens/intel multiplexed address timing
sab 82538 saf 82538 semiconductor group 225 figure 55 siemens/intel read cycle timing note 1: function of dtack is described logically as: dtack = ( cs x dack + rd x wr) x intai intai is an internally generated signal. note 2: drr is reset with the falling edge of rd during the last read access to rfifo.
sab 82538 saf 82538 semiconductor group 226 figure 56 siemens/intel write cycle timing note 1: function of dtack is described logically as: dtack = ( cs x dack + rd x wr) x intai intai is an internally generated signal. note 2: drt is reset with the falling edge of cs or dack if the last write access to xfifo is expected. however, drt will be activated again in the case of an access to any other register or fifo.
sab 82538 saf 82538 semiconductor group 227 figure 57 siemens/intel interrupt timing (slave mode) note 1: timing valid for active-high push-pull signal. timing for active-low push-pull signal is the same. in case of an open drain output, reset time (t23) depends on external devices. note 2: function of dtack is described logically as: dtack = ( cs x dack + rd x wr) x intai intai is an internally generated signal. it is generated if the interrupt acknowledge cycle is considered valid.
sab 82538 saf 82538 semiconductor group 228 figure 58 siemens/intel interrupt timing (daisy chaining) note 1: timing valid for active-high push-pull signal. timing for active-low push-pull signal is the same. in case of an open-drain output, reset times (t23, t31) depend on external devices. note 2: timing for cs, dack, int, inta and d7-d0 is similar to slave mode.
sab 82538 saf 82538 semiconductor group 229 siemens/intel bus interface and interrupt timing parameter no. symbol limit values unit min. max. address, bhe, dack setup time 1 t su(a) 15 ns address, bhe, dack hold time 2 t h(a) 0ns cs setup time 3 t su(s) 0ns cs hold time 3a t h(s) 0ns address, bhe stable before ale inactive 4 t su(a-ale) 20 ns address, bhe hold after ale inactive 5 t h(ale-a) 10 ns ale pulse width 6 t w(ale) 30 ns address latch setup time before cmd active 7 t su(ale) 0ns ale to command inactive delay 7a t rec(ale) 20 ns rd pulse width 8 t w(r) 90 ns rd control interval 9 t rec(r) 50 ns data valid after rd active 10 t a(r) 80 ns data hold after rd inactive 11 t v(r) 10 ns rd inactive to data bus tristate note 1 11a t dis(r) 40 ns drr low after rd active 12 t p(ddr) 65 ns wr pulse width 13 t w(w) 50 ns wr control interval 14 t rec(w) 35 ns data stable before wr inactive 15 t su(d) 30 ns note: not tested in production.
sab 82538 saf 82538 semiconductor group 230 data hold after wr inactive 16 t h(d) 10 ns drt low after cs, dack active 17 t dis(drt) 50 ns drt return to one after cs, dack inactive 18 t p(drt) 60 ns cs, dack inactive setup ( inta cycle) 19 t dis(s-int) 0ns cs, dack inactive hold ( inta cycle) 20 t inta-s 0ns inta pulse width 21 t w(inta) 75 ns inta control interval 22 t rec(inta) 30 ns int reset after last inta inactive 23 t inta-int 60 ns slave address (ie0, ie1, ie2) setup time 24 t su(ie) 10 ns slave address (ie0, ie1, ie2) hold time 25 t h(ie) 30 ns interrupt vector (d7-d0) valid after inta active 26 t a(vec) 50 ns interrupt vector (d7-d0) hold after inta inactive 27 t v(vec) 10 ns interrupt vector (d7-d0) hold after inta inactive 27a t h(vec) 40 ns ie0 low after ie1 low 28 t ie1l-ie0l 20 ns ie0 high after ie1 high 29 t ie1h-ie0h 20 ns ie0 low after int active 30 t intv-ie0l 10 ns int inactive after ie1 low 31 t dis(int) 25 ns note: 27a and 52a are not tested in production siemens/intel bus interface and interrupt timing (contd) parameter no. symbol limit values unit min. max.
sab 82538 saf 82538 semiconductor group 231 note: 27a and 52a are not tested in production 94 tbd in 5.95 int reactivated after ie1high 32 t ie1h-intv 25 ns ie0 high after int reset 33 t int-ie0h 30 ns dtack active after command active 50 t p(dtk) 60 ns dtack active after inta active 51 t p(int-dtk) 35 ns dtack hold after command inactive 52 t v(dtk) 10 ns dtack high to dtack high impedance 52a t h(dtk) 40 ns dtack hold after inta inactive 53 t v(int-dtk) 10 ns wr to rd control interval 94 t 94 100 ns siemens/intel bus interface and interrupt timing (contd) parameter no. symbol limit values unit min. max.
sab 82538 saf 82538 semiconductor group 232 5.4.1.2 motorola bus interface mode figure 59 motorola read cycle timing note 1: function of dtack is described logically as: dtack = cs x dack x intai + ds x r/ w) i.e. in accordance with common specifications of motorola read accesses the timing of dtack is normally determined by ds. note 2: drr is reset with the falling edge of ds during the last read access to rfifo.
sab 82538 saf 82538 semiconductor group 233 figure 60 motorola write cycle timing
sab 82538 saf 82538 semiconductor group 234 note 1: function of dtack is described logically as: dtack = cs x dack x intai + ds x r/w i.e. in accordance with common specifications of motorola accesses dtack goes active if either cs or dackx is active and r/w goes low dtack goes inactive if cs and dackx are inactive or write r/w goes high. to guarantee correct function in the case of write bursts signals cs and dackx have to be inactive after each write access (e.g. by deriving them from the address strobe as). note 2: drt is reset with the falling edge of cs or dack if the last write access to xfifo is expected. however, drt will be activated again in the case of an access to any other register or fifo. figure 61 motorola w to r control interval
sab 82538 saf 82538 semiconductor group 235 figure 62 motorola interrupt timing (slave mode) note 1: timing valid for active-high push-pull signal. timing for active-low push-pull signal is the same. in the case of an open-drain output, reset times (t23, t31) depend on external devices. note 2: function of dtack is described logically as: dtack = cs x dack x intai + ds x r/w intai is an internal signal. it is generated if the interrupt acknowledge cycle is considered valid.
sab 82538 saf 82538 semiconductor group 236 figure 63 motorola interrupt timing (daisy chaining) note 1: timing valid for active-high push-pull signal. timing for active-low push-pull signal is the same. in the case of an open-drain output, reset times (t23, t31) depend on external devices. note 2: timing for cs, dack, int, inta, ds and d7-d0 is similar to slave mode.
sab 82538 saf 82538 semiconductor group 237 motorola bus interface timing and interrupt timing parameter no. symbol limit values unit min. max. address, ble, dack setup time before ds active 34 t su(a) 15 ns address, ble, dack hold after ds inactive 35 t h(a) 0ns cs active before ds active 36 t su(s) 0ns cs hold after ds inactive 36a t h(s) 0ns r/ w stable before ds active 37 t su(rw) 5ns r/ w hold after ds inactive 38 t h(rw) 0ns ds pulse width (read access) (write access) 39 39a t w(ds)r t w(ds)w 90 60 ns ns ds control interval 40 t rec(ds) 70 ns data valid after ds active(read access) 41 t a(ds) 80 ns data hold after ds inactive (read access) 42 t v(ds) 10 ns ds inactive to databus tristate (read access) note 1 42a t dis(ds) 40 ns drr low after ds active 43 t p(drr) 65 ns data stable before ds active (write access) 44 t su(d) 30 ns data hold after ds inactive (write access) 45 t h(d) 10 ns drt low after ds or dack active 46 t dis(drt) 50 ns drt return to one after cs or dack inactive 47 t p(drt) 50 ns cs, dack inactive setup before ds ( inta cycle) 19a t dis(s-inta) 20 ns cs, dack inactive hold after ds ( inta cycle) 20a t h(inta-s) 20 ns
sab 82538 saf 82538 semiconductor group 238 motorola bus interface timing and interrupt timing (contd) note: 49max, 50a and 52a are not tested in production. 95 tbd in 5.95 parameter no. symbol limit values unit min. max. inta control interval 22a t rec(inta) 30 ns int reset after last inta inactive 23 t inta-int 60 ns slave address (ie0, ie1, ie2) setup time 24 t su(ie) 10 ns slave address (ie0, ie1, ie2) hold time 25 t h(ie) 30 ns ie0 low after ie1 low 28 t ie1l-ie0l 20 ns ie0 high after ie1high 29 t ie1h-ie0h 20 ns ie0 low after int active 30 t intv-ie0l 10 ns int inactive after ie1 low 31 t dis(int) 25 ns int reactivated after ie1 high 32 t ie1h-intv 25 ns ie0 high after int reset 33 t int-ie0h 30 ns inta setup time 48 t su(inta) 0ns inta hold time 48a t h(inta) 0ns interrupt vector hold after ds or inta inactive 49 t v(vec) 10 40 ns dtack active delay 50 t p(dtk) 60 ns dtack active to data valid (read cycle) 50a t dtk-d 45 ns dtack hold after command inactive 52 t v(dtk) 10 ns dtack high to dtack high impedance 52a t h(dtk) 40 ns w to r control interval 95 t 95 100 ns
sab 82538 saf 82538 semiconductor group 239 5.4.2 parallel port timing figure 64 parallel port write access figure 65 parallel port read access
sab 82538 saf 82538 semiconductor group 240 parallel port timing 5.4.3 serial interface 5.4.3.1 clock input timing figure 66 clock timing parameter no. symbol limit values unit min. max. port output data valid after wr, ds inactive 54 t qv 80 ns port input data change to int active delay 55 t p(pv-int) 60 ns port input data stable before rd, ds active 56 t su(p) 20 ns port input data hold after rd, ds active 57 t h(p) 30 ns
sab 82538 saf 82538 semiconductor group 241 clock timing note 1: externally clocked: clock mode 0, 1 except async, bcr = 16. note 2: externally clocked: clock mode 4 except async, bcr = 16; master clock mode generally. note 3: internally clocked: hdlc, bisync: dpll + baud rate generator used. async all other clocking modes. parameter no. symbol limit values unit h h-10 min. max. min. max. rxclk clock period (note 1) (note 3) 58 t c(rxc) 480 50 100 50 ns ns rxclk high time (note 1) (note 3) 59 t w(rxch) 150 22 45 22 ns ns rxclk low time (note 1) (note 3) 60 t w(rxcl) 150 22 45 22 ns ns txclk clock period 61 t c(txc) 480 100 ns txclk high time 62 t w(txch) 150 45 ns txclk low time 63 t w(txcl) 150 45 ns xtal1 clock period (note 2) (note 3) 64 t c(xtal1) 480 75 100 75 ns ns xtal1 high time (note 2) (note 3) 65 t w(xtal1h) 150 35 45 35 ns ns xtal1 low time (note 2) (note 3) 66 t w(xtal1l) 150 35 45 35 ns ns
sab 82538 saf 82538 semiconductor group 242 5.4.3.2 receive cycle timing figure 67 receive cycle timing note 1: whichever supplies the clock: externally clocked by r clk or xtal1, or, internally derived from dpll, brg or bcr divider ( refer to table 5 ) note 2: nrz, nrzi and manchester coding note 3: fm0 and fm1 coding note 4: carrier detect auto start enabled (not for clock modes 1, 5)
sab 82538 saf 82538 semiconductor group 243 receive cycle timing parameter no. symbol limit values unit h h-10 min. max. min. max. receive data rate ext. clocked (except async, bcr = 16) 2 10 mbit/s int. clocked (hdlc, bisync: only dpll) 2 2 mbit/s int. clocked (all other internal modes) 2 2 mbit/s clock period ext. clocked (except async, bcr = 16) 67 t c(xc) 480 100 ns int. clocked (hdlc, bisync: only dpll) 480 480 ns int. clocked (all other internal modes) 480 480 ns receive data setup 68 t su(rxd) 10 10 ns receive data hold 69 t h(rxd) 30 30 ns carrier detect setup 70 t su(cd) 50 50 ns carrier detect hold 71 t h(cd) 30 30 ns cd status change to int delay 72 t cd-int t73 +60 t73 +60 ns
sab 82538 saf 82538 semiconductor group 244 5.4.3.3 transmit cycle timing figure 68 transmit cycle timing
sab 82538 saf 82538 semiconductor group 245 note 1: whichever supplies the clock: externally clocked by txclk, xtal1 or rxclk or, internally derived from dpll, brg or bcr divider ( refer to table 5 ). note 2: nrz and nrzi coding. note 3: fm0, fm1 and manchester coding. note 4: if output function is enabled ( refer to table 5 ). note 5: the timing shown is valid for normal operation and bus configuration mode 1. in bus configuration mode 2, rts and txd are shifted for 1/2 xclock period.
sab 82538 saf 82538 semiconductor group 246 transmit cycle timing parameter no. symbol limit values unit h h-10 min. max. min. max. transmit data rate ext. clocked (except async, bcr = 16) 2 10 mbit/s int. clocked (hdlc, bisync: only dpll) 2 2 mbit/s int. clocked (all other internal modes) 2 2 mbit/s clock period ext. clocked (except async, bcr = 16) 73 t c(xc) 480 100 ns int. clocked (hdlc, bisync: only dpll) 480 480 ns int. clocked (all other internal modes) 480 480 ns transmit data delay 74 t p(txd) 70 70 ns transmit data delay 74c 75 75 ns rxd to txd delay (sdlc loop, off loop state) 74a t p(rxd-txd) 50 50 ns clock output to transmit data delay 75 t p(xc-txd) C 30 20 C 30 20 ns collision data and cts setup time 76 t su(cxd) 10 10 ns collision data and cts hold time 77 t h(cxd) 30 30 ns request send delay normal operation bus configuration 78 t p(rts) 65 50 65 50 ns ns cts status change to int delay t cts-int t73 +60 t73 +60 ns
sab 82538 saf 82538 semiconductor group 247 5.4.3.4 strobe timing (clock mode 1) figure 69 strobe timing note 1: high impedance if t d is set to open drain function. otherwise, active high. note 2: normal operation and bus configuration mode 1. note 3: bus configuration mode 2.
sab 82538 saf 82538 semiconductor group 248 strobe timing note: 88 and 89 are not tested in production. parameter no. symbol limit values unit h h-10 min. max. min. max. receive strobe delay 80 t rxcl-rs 30 30 ns receive strobe setup 81 t su(rs) 30 30 ns receive strobe hold 82 t h(rs) 30 30 ns transmit strobe delay 83 t rxcl-xs 30 30 ns transmit strobe setup 84 t su(xs) 30 30 ns transmit strobe hold 85 t h(xs) 30 30 ns transmit data delay from clock 86 t p(rxc-txd) 65 65 ns transmit data delay from strobe 87 t p(xs-txd) 50 50 ns high impedance from clock 88 t dis(rxc) 70 70 ns high impedance from strobe 89 t dis(xs) 70 70 ns
sab 82538 saf 82538 semiconductor group 249 5.4.3.5 synchronization timing (clock mode 5) figure 70 synchronization timing note 1: normal operation and bus configuration mode 1. note 2: bus configuration mode 2.
sab 82538 saf 82538 semiconductor group 250 synchronization timing note: clock mode 5 only specified for versions sab 82538h-10. 5.4.4 reset timing reset timing parameter no. symbol limit values unit h h-10 min. max. min. max. sync pulse delay 90 t rxc-sync 30 ns sync pulse setup 91 t su(sync) 30 ns sync pulse hold 92 t h(sync) 25 ns time-slot control delay 93 t p(tslc) 20 75 ns xtal1 low time (note 2) (note 3) 66 t w(xtal1l) 150 45 ns ns parameter no. symbol limit values unit h h-10 min. max. min. max. res pulse width t w(res) 5000 5000 ns
sab 82538 saf 82538 semiconductor group 251 6 package outlines plastic package, p-mqfp-160 (smd) (plastic metric quad flat package) gpm05247 dimensions in mm sorts of packing package outlines for tubes, trays etc. are contained in our data book package information smd = surface mounted device
sab 82538 saf 82538 semiconductor group 252 7 appendix errata sheet sab 82538h, version v2.2 1. general the following errata should be noted when version 2.2 of the escc8 (sab 82538) is used. a. in clock mode the rts signal is deactivated after the transmission of the second last bit (instead of the last) of a closing flag (or the last character of a block of characters), if that second last bit is the last bit of the a time-slot window. in other words, rts is inactive during the transmission of the last bit, transmitted in the next time-slot window. see figure below. furthermore, the alls (all sent) interrupt status is generated after the transmission of the second last bit, one clock period after the deactivation of rts.
sab 82538 saf 82538 semiconductor group 253 recommendation: do not use rts in clock mode 5 e.g. to enable drivers for txd in a bus configuration. (for example, use an arrangement of the type shown in the figure below instead.) b. the maximum achievable bit rates in internal timing modes (where bit timing is extracted from the data by the escc8 by means of the internal dpll) are: 1.2 mbit/s when rxclk is used as clock source for the baud rate generator (clock modes 2, 3). 0.8 mbit/s when xtal1 (1, 2) is used to supply the clock source for the baud rate generator (clock modes 6, 7).

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